82551QM datasheet(39/120 Pages) INTEL

39 / 120 page

Networking Silicon — 82551QM

Datasheet

Note:

Flash accesses must always be assembled or disassembled by the 82551QM whenever the access is

greater than a byte-wide access. Due to slow access times to a typical Flash and to avoid violating

PCI bus holding specifications (no more than 16 wait states inserted for any cycles that are not

system initiation cycles), the maximum data size is either one word or one byte for a read operation

and one byte only for a write operation.

Note:

In mobile applications, the MDMCS# pin enables the modem controller or Flash device.

5.7

Serial EEPROM Interface

The serial EEPROM stores configuration data for the 82551QM and is a serial in/serial out device.

The 82551QM supports either a 64-register or 256-register size EEPROM and automatically

detects the EEPROM’s size. A 256-word EEPROM device is required for a Cardbus system and

contains the CIS information. A 256-word EEPROM device is also required for a TCO enabled

system to hold the heartbeat packet. The EEPROM should operate at a frequency of at least 1 MHz.

All accesses, either read or write, are preceded by a command instruction to the device. The

address field is six bits for a 64-register EEPROM or eight bits for a 256-register EEPROM. The

end of the address field is indicated by a dummy zero bit from the EEPROM, which indicates the

entire address field has been transferred to the device. An EEPROM read instruction waveform is

shown in the figure below.

The 82551QM can also use the EEPROM for heartbeat packet transmission (systems without a

TCO controller are also supported). In these designs, the EEPROM is accessed through time

windows autonomously by the 82551QM hardware. During these time windows, the 82551QM

will respond with a PCI Retry to both EEPROM and Flash accesses.

The 82551QM performs an automatic read of five words (0h, 1h, 2h, Ah, and Dh) of the EEPROM

after the de-assertion of Reset. It may read six more words (Bh, Ch, FBh, FCh, FDh, and FEh) if

the modem bit is set in the EEPROM (word Ah, bit 0). Refer to the 82551QM/ER/IT EEPROM

Map and Programming Information for more details.

Figure 10. 64-Word EEPROM Read Instruction Waveform

EECS

EESK

EEDI

EEDO

READ OP code

82551QM Datasheet(PDF) 39 Page - Intel Corporation