9000 datasheet(32/108 Pages) INTEL

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Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet

Electrical Specifications

Warm Reset Sequence:

• PWRGOOD remains high throughout the entire sequence, as power is already

available and stable to the processor.

• The configuration pins (A[21:17]#) must be asserted the entire time RESET# is

asserted.

• The duration from the assertion of RESET# to the deassertion of RESET# must be 1

millisecond minimum.

• After RESET# is deasserted, the configuration pins must remain valid for two

BCLKs (minimum) to three BCLKs (maximum).

• BCLK is shown as a time reference to the BCLK period. It is not a requirement that

this is BCLKn or BCLKp signal.

• Configuration signals other than A[21:17]# must be asserted four BCLKs prior to

the deasserted edge of RESET# and must remain valid for two BCLKs (minimum) to

three BCLKs (maximum) after the deasserted edge of RESET#.

Figure 2-6 outlines the timing relationship between the configuration pins, RESET# and

PWRGOOD for warm reset.

Figure 2-6. System Bus Reset and Configuration Timings for Warm Reset

000777b

BCLK

PWRGOOD

RESET#

Bus Ratio

(A[21:17]#)

TA = 1.15 ns minimum; (set up time to BCLK for deassertion edge of RESET#)

TB = 1 ms minimum for warm reset

TD = 2 BCLKs minimum, 3 BCLKs maximum

TE = 4 BCLKs minimum

TF = 2 BCLKs minimum, 3 BCLKs maximum

Additional

Configuration

Signals

TC = Bus ratio signals must be asserted no later than RESET#

-2

-1

-4

-3

9000 Datasheet(PDF) 32 Page - Intel Corporation