360J datasheet(55/68 Pages) INTEL

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Datasheet

Package Mechanical Specifications and Pin Information

4.2

Alphabetical Signals Reference

Table 16.

Signal Description (Sheet 1 of 8)

Name

Type

Description

A[31:3]#

Input/

Output

A[31:3]# (Address) define a 232-byte physical memory address

space. In sub-phase 1 of the address phase, these pins transmit the

address of a transaction. In sub-phase 2, these pins transmit

transaction type information. These signals must connect the

appropriate pins of both agents on the Intel® Celeron® M processor

FSB. A[31:3]# are source synchronous signals and are latched into

the receiving buffers by ADSTB[1:0]#. Address signals are used as

straps which are sampled before RESET# is deasserted.

A20M#

Input

If A20M# (Address-20 Mask) is asserted, the processor masks

physical address bit 20 (A20#) before looking up a line in any

internal cache and before driving a read/write transaction on the

bus. Asserting A20M# emulates the 8086 processor's address wrap-

around at the 1-Mbyte boundary. Assertion of A20M# is only

supported in real mode.

A20M# is an asynchronous signal. However, to ensure recognition of

this signal following an Input/Output write instruction, it must be

valid along with the TRDY# assertion of the corresponding Input/

Output Write bus transaction.

ADS#

Input/

Output

ADS# (Address Strobe) is asserted to indicate the validity of the

transaction address on the A[31:3]# and REQ[4:0]# pins. All bus

agents observe the ADS# activation to begin parity checking,

protocol checking, address decode, internal snoop, or deferred reply

ID match operations associated with the new transaction.

ADSTB[1:0]#

Input/

Output

Address strobes are used to latch A[31:3]# and REQ[4:0]# on their

rising and falling edges. Strobes are associated with signals as

shown below.

BCLK[1:0]

Input

The differential pair BCLK (Bus Clock) determines the FSB frequency.

All FSB agents must receive these signals to drive their outputs and

latch their inputs.

All external timing parameters are specified with respect to the rising

edge of BCLK0 crossing VCROSS.

BNR#

Input/

Output

BNR# (Block Next Request) is used to assert a bus stall by any bus

agent who is unable to accept new bus transactions. During a bus

stall, the current bus owner cannot issue any new transactions.

BPM[2:0]#

BPM[3]

Output

Input/

Output

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance

monitor signals. They are outputs from the processor which indicate

the status of breakpoints and programmable counters used for

monitoring processor performance. BPM[3:0]# should connect the

appropriate pins of all Celeron M FSB agents.This includes debug or

performance monitoring tools.

Signals

Associated

Strobe

REQ[4:0]#, A[16:3]#

ADSTB[0]#

A[31:17]#

ADSTB[1]#

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