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L9951XP Datasheet(PDF) 15 Page - STMicroelectronics |
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L9951XP Datasheet(HTML) 15 Page - STMicroelectronics |
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15 / 36 page ![]() L9951 / L9951XP Electrical specifications Doc ID 14173 Rev 8 15/36 Note: DI timing parameters tested in production by a passed/failed test: Tj= -40°C/+25°C: SPI communication @2MHZ. Tj= +125°C: SPI communication @1.25MHZ. tr in Rise time of input signal DI, CLK, CSN VCC = 5V 100 ns tf in Fall time of input signal DI, CLK, CSN VCC = 5V 100 ns 1. See Figure 3 and Figure 4 Table 14. DI timing(1) (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Table 15. DO Symbol Parameter Test condition Min. Typ. Max. Unit VDOL Output low level VCC = 5 V, ID = -4mA 0.2 0.4 V VDOH Output high level VCC = 5 V, ID = 4 mA VCC -0.4 VCC -0.2 V IDOLK Tristate leakage current VCSN = VCC, 0V < VDO < VCC -10 10 µA CDO (1) 1. Value of input capacity is not measured in production test. Parameter guaranteed by design. Tristate input capacitance VCSN = VCC, 0V < VCC < 5.3V 10 15 pF Table 16. DO timing(1) 1. See Figure 5 and Figure 6. Symbol Parameter Test condition Min. Typ. Max. Unit tr DO DO rise time CL = 100 pF, Iload = -1mA 80 140 ns tf DO DO fall time CL = 100 pF, Iload = 1mA 50 100 ns ten DO tri L DO enable time from tristate to low level CL = 100 pF, Iload = 1mA pull-up load to VCC 100 250 ns tdis DO L tri DO disable time from low level to tristate CL = 100 pF, Iload = 4 mA pull-up load to VCC 380 450 ns ten DO tri H DO enable time from tristate to high level CL =100 pF, Iload = -1mA pull-down load to GND 100 250 ns tdis DO H tri DO disable time from high level to tristate CL = 100 pF, Iload = -4mA pull-down load to GND 380 450 ns td DO DO delay time VDO < 0.3 VCC, VDO > 0.7VCC, CL = 100pF 50 250 ns |
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