L9951XP datasheet(25/36 Pages) STMICROELECTRONICS

25 / 36 page

L9951 / L9951XP

Functional description of the SPI

Doc ID 14173 Rev 8

25/36

Current monitor

select bits

Following current image

(1/10.000) of the HS driver

will be multiplexed to CM

output:

Temperature

warning

This bit is for information

purpose only. It can be used

for a thermal management by

the microcontroller to avoid a

thermal shutdown.

Not ready bit

After switching the device from

standby mode to active mode

an internal timer is started to

allow charge pump to settle

before the outputs can be

activated. This bit is cleared

automatically after start up

time has finished. Since this bit

is controlled by internal clock it

can be used for synchronizing

testing events (e.g. measuring

filter times).

Not used

OUT5 - HS

on/off

If a bit is set the selected

output driver is switched on.

If the corresponding PWM

enable bit is set (Input

activated if PWM input

signal is high. The outputs of

OUT1-OUT3 are half

bridges. If the bits of HS-

and LS-driver of the same

half bridge are set, the

internal logic prevents that

both drivers of this output

stage can be switched on

simultaneously in order to

avoid a high internal current

from VS to GND.

OUT5-HS

over - current

In case of an over-current

event the corresponding status

bit is set and the output driver

is disabled. If the over-current

recovery enable bit is set

(Input Register 1) the output

will be automatically

reactivated after a delay time

resulting in a PWM modulated

current with a programmable

duty cycle (Bit 13).

If the over-current recovery bit

is not set the microcontroller

has to clear the over-current bit

(reset bit) to reactivate the

output driver.

OUT4 - HS

on/off

OUT4-HS

over - current

OUT3 - HS

on/off

OUT3-HS

over - current

OUT3 - LS

on/off

OUT3-LS

over - current

OUT2 - HS

on/off

OUT2-HS

over - current

OUT2 - LS

on/off

OUT2-LS

over - current

OUT1 - HS

on/off

OUT1-HS

over - current

OUT1 - LS

on/off

OUT1-LS

over - current

No error bit

A logical NOR-combination of

all bits 1 to 14 in both status

registers. If bit 14 (disable

open-load) is set, the open-

load status will be ignored.

Table 19.

SPI - Input data and status register 0 (continued)

Input register 0 (write)

Status register 0 (read)

Bit

Name

Comment

Name

Comment

Bit 11 Bit 10 Bit 9

Output

000

OUT1

001

OUT2

010

OUT3

011

OUT4

100

OUT5

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