L9951TR datasheet(16/36 Pages) STMICROELECTRONICS

16 / 36 page

Electrical specifications

L9951 / L9951XP

16/36

Doc ID 14173 Rev 8

Figure 3.

SPI - transfer timing diagram

Figure 4.

SPI - input timing

Table 17.

EN, CSN timing(1)

See Figure 7

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

tEN_CSN_LO

Minimum EN high before

sending first SPI frame, i.e.

CSN going low

Transfer of SPI-command

to input register

µs

tCSN_HI,min

Minimum CSN HI time

between two SPI frames

Transfer of SPI-command

to input register

µs

time

CSN high to low: DO enabled

actual data

DI: data will be accepted on the rising edge of CLK signal

new data

CSN

CLK

e.g.OUT1

DO: data will change on the falling edge of CLK signal

status information

fault bit

CSN low to high: actual data is

transfered to output power switches

old data

9 10 11

012

13 14 15

actual data

10 11

012

13 14 15

10 11

012

13 14 15

0.8 VCC

0.2 VCC

Valid

CSN

CLK

tset CSN

tCLKH

set CLK

tCLKL

thold DI

tset DI

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