R29 datasheet(114/473 Pages) RENESAS

114 / 473 page

R8C/28 Group, R8C/29 Group

10. Clock Generation Circuit

Rev.2.10

Sep 26, 2008

Page 95 of 441

REJ09B0279-0210

Figure 10.16 shows the State Transitions in Power Control Mode (When the CM01 bit in the CM0 register is set

to 0 (XIN clock)). Figure 10.17 shows the State Transitions in Power Control Mode (When the CM01 bit in the

CM0 register is set to 1 (XCIN clock)).

Figure 10.16

State Transitions in Power Control Mode (When the CM01 bit in the CM0 register is

set to 0 (XIN clock))

CM10 = 1

CPU operation stops

Stop mode

State Transitions in Power Control Mode

(When the CM01 bit in the CM0 register is set to 0 (XIN clock))

Reset

Wait mode

Low-speed on-chip oscillator mode

CM14 = 0

OCD2 = 1

FRA01 = 0

High-speed on-chip oscillator mode

OCD2 = 1

FRA00 = 1

FRA01 = 1

High-speed clock mode

CM05 = 0

CM13 = 1

OCD2 = 0

Standard operating mode

CM14 = 0

OCD2 = 1

FRA01 = 0

CM05 = 0

CM13 = 1

OCD2 = 0

CM05 = 0

CM13 = 1

OCD2 = 0

OCD2 = 1

FRA00 = 1

FRA01 = 1

FRA00 = 1

FRA01 = 1

CM14 = 0

FRA01 = 0

All oscillators stop

Interrupt

WAIT instruction

Interrupt

CM05: Bit in CM0 register

CM13, CM14: Bits in CM1 register

OCD2: Bit in OCD register

FRA00, FRA01: Bits in FRA0 register

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