R29 datasheet(136/473 Pages) RENESAS

136 / 473 page

R8C/28 Group, R8C/29 Group

12. Interrupts

Rev.2.10

Sep 26, 2008

Page 117 of 441

REJ09B0279-0210

12.2

INT Interrupt

12.2.1

INTi Interrupt (i = 0, 1, 3)

The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN

POL bit in the INTiIC register.

Inputs can be passed through a digital filter with three different sampling clocks.

Table 12.6 lists the Pin Configuration of INT Interrupt. Figure 12.12 shows the INTEN Register. Figure 12.13

shows the INTF Register.

NOTE:

1. The INT1 pin is selected by the INT1SEL bit in the PMR register and the TIOSEL bit in the TRAIOC

Figure 12.12

INTEN Register

Table 12.6

Pin Configuration of INT Interrupt

Pin name

Input/Output

Function

INT0 (P4_5)

Input

INT0 interrupt input, Timer RB external trigger input,

Timer RC pulse output forced cutoff input

INT1 (P1_5 or P1_7)(1)

Input

INT1 interrupt input

INT3 (P3_3)

Input

INT3 interrupt input

External Input Enable Register

Symbol

Address

After Reset

INTEN

00F9h

00h

Bit Symbol

Bit Name

Function

INT0

_____

input enable bit

INT0

_____

input polarity select bit(1,2)

INT1

_____

input enable bit

INT1

_____

input polarity select bit(1,2)

INT3

_____

input enable bit

INT3

_____

input polarity select bit(1,2)

NOTES:

INT3PL

b3 b2 b1 b0

b7 b6 b5 b4

INT0EN

INT1PL

0 : One edge

1 : Both edges

INT3EN

When setting the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling

edge).

The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to 12.6.4

Changing Interrupt Sources.

0 : Disable

1 : Enable

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

INT0PL

INT1EN

0 : Disable

1 : Enable

0 : Disable

1 : Enable

—

(b5-b4)

Set to 0.

Reserved bits

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