R5F36CAMNFB datasheet(52/94 Pages) RENESAS

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REJ03B0277-0100 Rev.1.00 Jul.15, 2009

Page 50 of 90

M16C/6C Group

5. Electrical Characteristics

5.1.6

Flash Memory Electrical Characteristics

Notes:

Set the PM17 bit in the PM1 register to 1 (one wait).

When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in

the PM1 register to 1 (one wait)

Set the PM17 bit in the PM1 register to 1(one wait). A wait is not necessary when using 125 kHz on-chip

oscillator clock or sub clock as the CPU clock source.

Notes:

VCC1 = 2.7 to 5.5 V at Topr = 0 to 60°C (option: -40°C to 85°C), unless otherwise specified.

Definition of program and erase cycles

The program and erase cycles refer to the number of per-block erasures.

If the program and erase cycles are n (n=1,000), each block can be erased n times.

For example, if a 4 Kbyte block is erased after writing two word data 1,024 times, each to a different address, this

counts as one program and erase cycles. Data cannot be written to the same address more than once without

erasing the block (rewrite prohibited).

Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).

In a system that executes multiple programming operations, the actual erasure count can be reduced by writing

to sequential addresses in turn so that as much of the block as possible is used up before performing an erase

operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be

minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to

retain data on the erasure cycles of each block and limit the number of erase operations to a certain number.

If an error occurs during block erase, attempt to execute the clear status register command, then execute the

block erase command at least three times until the erase error does not occur.

Customers desiring program/erase failure rate information should contact their Renesas technical support

representative.

The data hold time includes time that the power supply is off or the clock is not supplied.

Table 5.9

CPU Clock When Operating Flash Memory (f(BCLK))

Symbol

Parameter

Conditions

Standard

Unit

Min.

Typ.

Max.

CPU rewrite mode

10 (1)

MHz

f(SLO

W_R)

Slow read mode

5(3)

MHz

Low current consumption read mode

kHz

Data flash read

2.7 V

≤ V

CC1 ≤ 3.0 V

16 (2)

MHz

3.0 V < VCC1 ≤ 5.5 V

20 (2)

MHz

Table 5.10

Flash Memory (Program ROM 1, 2) Electrical Characteristics

Symbol

Parameter

Conditions

Standard

Unit

Min.

Typ.

Max.

Program/erase cycles (2, 4, 5)

VCC1 = 3.3 V, Topr = 25°C

1,000 (3)

times

Two words program time

VCC1 = 3.3 V, Topr = 25°C

150

4000

μs

Lock bit program time

VCC1 = 3.3 V, Topr = 25°C

3000

μs

Block erase time

VCC1 = 3.3 V, Topr = 25°C

0.2

3.0

Program, erase voltage

2.7

5.5

Read voltage

2.7

5.5

Program, erase temperature

°C

tPS

Flash Memory Circuit Stabilization Wait Time

μs

Data hold time (7)

Ambient temperature = 55

°C

year

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