TC1797 datasheet(39/190 Pages) INFINEON

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TC1797

Introduction

Data Sheet

V1.1, 2009-04

2.5.2

High-Speed Synchronous Serial Interfaces

The TC1797 includes two High-Speed Synchronous Serial Interfaces, SSC0 and SSC1.

Both SSC modules have the same functionality.

Figure 6 shows a global view of the Synchronous Serial interface (SSC).

Figure 6

General Block Diagram of the SSC Interface

The SSC supports full-duplex and half-duplex serial synchronous communication up to

45 Mbit/s (@ 90 MHz module clock, Master Mode). The serial clock signal can be

generated by the SSC itself (Master Mode) or can be received from an external master

(Slave Mode). Data width, shift direction, clock polarity and phase are programmable.

This allows communication with SPI-compatible devices. Transmission and reception of

data are double-buffered. A shift clock generator provides the SSC with a separate serial

clock signal. One slave select input is available for slave mode operation. Eight

programmable slave select outputs (chip selects) are supported in Master Mode.

MCB06058_mod

Clock

Control

Address

Decoder

Interrupt

Control

SSC

Module

(Kernel)

MRSTB

MTSR

Master

RIR

TIR

EIR

SLSI[7:1]

SLSO[7:0]

MRST

MTSR

SCLK

MRSTA

MTSRB

MRST

MTSRA

SCLKB

SCLK

SCLKA

Slave

Master

Slave

Master

Port

Control

CLC

Enable

M/S Select

DMA Requests

SLSOANDO[7:0]

SLSOANDI[7:0]

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