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TC1797 Datasheet(PDF) 22 Page - Infineon Technologies AG |
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TC1797 Datasheet(HTML) 22 Page - Infineon Technologies AG |
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22 / 190 page ![]() TC1797 Introduction Data Sheet 18 V1.1, 2009-04 2.3 On-Chip System Units The TC1797 microcontroller offers several versatile on-chip system peripheral units such as DMA controller, embedded Flash module, interrupt system and ports. 2.3.1 Flexible Interrupt System The TC1797 includes a programmable interrupt system with the following features: Features • Fast interrupt response • Independent interrupt systems for CPU and PCP • Each SRN can be mapped to the CPU or PCP interrupt system • Flexible interrupt-prioritizing scheme with 255 interrupt priority levels per interrupt system 2.3.2 Direct Memory Access Controller The TC1797 includes a fast and flexible DMA controller with 16 independant DMA channels (two DMA Move Engines). Features • 8 independent DMA channels – 8 DMA channels in the DMA Sub-Block – Up to 16 selectable request inputs per DMA channel – 2-level programmable priority of DMA channels within the DMA Sub-Block – Software and hardware DMA request – Hardware requests by selected on-chip peripherals and external inputs • 3-level programmable priority of the DMA Sub-Block at the on chip bus interfaces • Buffer capability for move actions on the buses (at least 1 move per bus is buffered) • Individually programmable operation modes for each DMA channel – Single Mode: stops and disables DMA channel after a predefined number of DMA transfers – Continuous Mode: DMA channel remains enabled after a predefined number of DMA transfers; DMA transaction can be repeated – Programmable address modification – Two shadow register modes (with / w/o automatic re-set and direct write access). • Full 32-bit addressing capability of each DMA channel – 4 Gbyte address range – Data block move supports > 32 Kbyte moves per DMA transaction – Circular buffer addressing mode with flexible circular buffer sizes • Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit • Register set for each DMA channel |
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