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ISL6366 Datasheet(PDF) 19 Page - Intersil Corporation |
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ISL6366 Datasheet(HTML) 19 Page - Intersil Corporation |
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19 / 44 page ![]() ISL6366 19 FN6964.0 January 3, 2011 L/DCR OR ESL/RSEN MATCHING Assuming the compensator design is correct, Figure 11 shows the expected load transient response waveforms if L/DCR or ESL/RSEN is matching the R-C time constant. When the load current IOUT has a square change, the output voltage VOUT also has a square response, except for the overshoot at load release. However, there is always some PCB contact impedance of current sensing components between the two current sensing points; it hardly accounts into the L/DCR or ESL/RSEN matching calculation. Fine tuning the matching is necessarily done in the board level to improve overall transient performance and system reliability. If the R-C timing constant is too large or too small, VC(s) will not accurately represent real-time IOUT(s) and will worsen the transient response. Figure 12 shows the load transient response when the R-C timing constant is too small. VOUT will sag excessively upon load insertion and may create a system failure or early overcurrent trip. Figure 13 shows the transient response when the R-C timing constant is too large. VOUT is sluggish in drooping to its final value. There will be excessive overshoot if load insertion occurs during this time, which may potentially hurt the CPU reliability. Channel-Current Balance for VR0 The sensed current In from each active channel is summed together and divided by the number of active channels. The resulting average current IAVG provides a measure of the total load current. Channel current balance is achieved by comparing the sensed current of each channel to the average current to make an appropriate adjustment to the PWM duty cycle of each channel with Intersil’s patented current-balance method. Channel current balance is essential in achieving the thermal advantage of multiphase operation. With good current balance, the power loss is equally dissipated over multiple devices and a greater area. Voltage Regulation The compensation network shown in Figure 14 assures that the steady-state error in the output voltage is limited only to the error in the reference voltage (DAC & OFFSET) and droop current source, remote sense, and error amplifier. The sensed average current IDROOP is tied to FB internally and will develop voltage drop across the resistor between FB and VOUT for droop control. This current can be disconnected from the FB node by tying RFS_DRP high to VCC for non-droop applications. The output of the error amplifier, VCOMP, is compared to the internal sawtooth waveforms to generate the PWM signals. The PWM signals control the timing of the Intersil MOSFET drivers and regulate the converter output to the specified reference voltage. The ISL6366 does not have a unity gain amplifier in between the feedback path and error amplifier. For remote sensing, connect the microprocessor sensing pins to the non-inverting input, FB, via the feedback resistor (RFB), and inverting input, RGND, of the error amplifier. This configuration effectively removes the voltage error encountered when measuring the output voltage relative to the local controller ground reference point. VSEN should connect to remote sensing’s positive rail as well for over voltage protection. A digital-to-analog converter (DAC) generates a reference voltage, which is programmable via SVID bus. The DAC decodes the SVID set command into one of the discrete voltages shown in Table 4. In addition, the output voltage can be margined in ±5mV step between -640mV and 635mV, as shown in Table 5, via SVID set FIGURE 11. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS IOUT VOUT FIGURE 12. LOAD TRANSIENT RESPONSE WHEN R-C TIME CONSTANT IS TOO SMALL IOUT VOUT FIGURE 13. LOAD TRANSIENT RESPONSE WHEN R-C TIME CONSTANT IS TOO LARGE IOUT VOUT FIGURE 14. OUTPUT VOLTAGE AND LOAD-LINE REGULATION IDROOP EXTERNAL CIRCUIT COMP RC RFB FB - + VDROOP ERROR VCOMP CC - + VOUT RGND AMPLIFIER + + VID & OFFSET OVP - + - + VSEN ISL6366 DAC |
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