AT89LP51 datasheet(66/113 Pages) ATMEL

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3709B–MICRO–12/10

AT89LP51/52 - Preliminary

Mode 0 transfers data LSB first whereas SPI or TWI are generally MSB first. Emulation of these

interfaces may require bit reversal of the transferred data bytes. The following code example

reverses the bits in the accumulator:

EX:

MOV

R7, #8

REVRS: RLC

; C << msb (ACC)

XCH

A, R6

RRC

; msb (ACC) >> B

XCH

A, R6

DJNZ R7, REVRS

14.5.2

Three-Wire (Full-Duplex) Mode

Three-Wire Mode is similar to Two-Wire except that the shift data input and data output are sep-

arated for full-duplex operation. Three-Wire Mode is enabled by setting the SPEN bit in TCONB.

Transmission is initiated by any instruction that uses SBUF as a destination register. The “write

to SBUF” signal also loads a “1” into the 9th position of the transmit shift register and tells the TX

Control Block to begin a transmission. The internal timing is such that one full bit slot may elapse

between “write to SBUF” and activation of SEND.

SEND transfers the output of the shift register to the alternate output function line of P1.5, and

also transfers Shift Clock to the alternate output function line of P1.7. As data bits shift out to the

right, “0”s come in from the left. When the MSB of the data byte is at the output position of the

shift register, the “1” that was initially loaded into the 9th position is just to the left of the MSB,

and all positions to the left of that contain “0”s. This condition flags the TX Control block to do

one last shift, then deactivate SEND and set TI.

Reception occurs simultaneously with transmission if REN = 1. Data is input from P1.6. When

REN = 1 any write to SBUF causes the RX Control unit to write the bits 11111110B to the

receive shift register and activates RECEIVE in the next clock phase. As data bits come in from

the right, “1”s shift out to the left. When the “0” that was initially loaded into the right-most posi-

tion arrives at the left-most position in the shift register, it flags the RX Control block to do one

last shift and load SBUF. Then RECEIVE is cleared and RI is set. When REN = 0, the receiver is

not enabled. When a transmission occurs, SBUF will not be updated and RI will not be set even

though serial data is received on P1.6.

The relationship between the shift clock and data is identical to Two-Wire mode as listed in

Table 14-5 and shown in Figure . Three-Wire mode uses different I/Os from Two-Wire mode and

can be connected to SPI slave devices as shownin Figure 14-4. It is possible to time share the

UART hardware between SPI devices connected on P1 and UART devices on P3 with the

caveat that any asynchronous receptions on the RXD pin will be ignored while the UART is in

Mode 0.

Figure 14-4. SPI Connections for UART Mode 0

8-Bit Shift Register

Master

Slave

MSB

LSB

MSB

LSB

8-Bit Shift Register

MISO

MOSI

GPIO

SCK

Clock

Generator

AT89LP52

AT89LP51 Datasheet(PDF) 66 Page - ATMEL Corporation

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