M48T128Y, M48T128V

Operation modes

Doc ID 5746 Rev 6

7/23

2

Operation modes

Figure 3 on page 6 illustrates the static memory array and the quartz controlled clock

oscillator. The clock locations contain the year, month, date, day, hour, minute, and second

in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day

months are made automatically. Byte 1FFF8h is the clock control register. This byte controls

user access to the clock information and also stores the clock calibration setting. The seven

clock bytes (1FFFFh - 1FFF8h) are not the actual clock counters, they are memory locations

consisting of BiPORT™ READ/WRITE memory cells within the static RAM array. The

M48T128Y/V includes a clock control circuit which updates the clock bytes with current

information once per second. The information can be accessed by the user in the same

manner as any other location in the static memory array. The M48T128Y/V also has its own

power-fail detect circuit. This control circuitry constantly monitors the supply voltage for an

operation until valid power is restored.

Table 2.

Operating modes

Note:

Mode

E

G

W

DQ0-DQ7

Power

Deselect

4.5 to 5.5 V

or

3.0 to 3.6 V

X

X

High Z

Standby

WRITE

Active

READ

Active

READ

High Z

Active

Deselect

(1)

1.

See Table 11 on page 18 for details.

X

X

X

High Z

CMOS standby

Deselect

X

X

X

High Z

Battery backup mode