iC-MB3

BiSS INTERFACE MASTER, 1-Chan./3-Slaves

Rev D1, Page 16/26

Configuration Register Communication

Address

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

224

Not used

-

-

-

----

-

225

Not used

-

-

-

----

-

226

Start Address

WNR

REGADR(6:0)

227

Count Of Bytes

-

-

REGNUM(5)

REGNUM(4:0)

228

Channel Select

CHSEL(8:1)

229

SlaveID

-

REGVERS

SLAVEID(2:0)

-

-

-

Configuration Master

Address

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

230

Frequency Division

FREQ(7:0)

231

Not used

-

-

-

-

-

-

-

-

232

Frequency Division

AutoGetsens

FREQAGS(7:0)

233

Not used

-

-

-

-

-

-

-

-

Device ID

234

Revision

0

0

0

0

0

0

1

0

235

Type

1000 0011b

Configuration Channel

236

Slave Location

SLAVELOC(8:1)

237

Mode of Operation

SELSSI4

BiSSMOD4

SELSSI3

BiSSMOD3

SELSSI2

BiSSMOD2

SELSSI1

BiSSMOD1

238

Mode of Operation

SELSSI8

BiSSMOD8

SELSSI7

BiSSMOD7

SELSSI6

BiSSMOD6

SELSSI5

BiSSMOD5

239

Not used

-

-

--

--

-

-

Key to the configuration bits:

S

SELSSI:

Type of protocol: BiSS (0), SSI (1)

S

BiSSMOD:

BiSS protocol model: BiSS model A or B (0), BiSS-A/S (1)

Status Information and Command Register

Address

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

240

Status Information

nERR

nWDERR

d

nSENSERR

nREGERR

REGEND

d

EOT

241

Validity Messages

1,2)

SVALID4

d

SVALID3

d

SVALID2

d

SVALID1

d

242

Validity Messages

1,2)

SVALID8

d

SVALID7

d

SVALID6

d

SVALID5

d

243

Register

Messages

CDM

TIMEOUT

REG

2, 4)

REG-

BYTES(5)

REGBYTES(4:0)

244

Command

Register

BREAK

UCREAD-

SENS

SWRAM-

BANK

INIT

REGCMD

GETSENS0

GETSENS1

AGS

245

Control Flages

MAv0

MAf0

MAvS

MAfS

reserved

IDDQ

3)

IFTEST

3)

CLKENI

246

Not used

-

-

-

----

-

247

Not used

-

-

-

----

-

248

Channel Status

REG4

SL4

REG3

SL3

REG2

SL2

REG1

SL1

249

Channel Status

REG8

SL8

REG7

SL7

REG6

SL6

REG5

SL5

250...255

Not used

-

-

-

----

-

Reserved addresses for master devices featuring a higher slave or channel count, or more memory for register data.

1)

Any attempt to write to this register sets register values to 0.

2)

Two memory banks available.

3)

iC-Haus device test only, set to 0.

4)

For iC-MB3 the register bit REG is equal to REG1.

d

Bit not relevant (don’t care).