iC-MFN

8-FOLD FAIL-SAFE N-FET DRIVER

Rev A2, Page 3/13

PACKAGES QFN24 4 mm x 4 mm to JEDEC

PIN CONFIGURATION QFN24

(top view)

7

8

9

10

11

1

2

3

4

5

13

14

15

21

22

6

12

16

17

19

20

18

23

24

MFN

code...

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PIN FUNCTIONS

No. Name Function

1 OUT1 Output channel 1

2 VB

Supply Voltage

3 VBR

Supply Voltage (R)

4 EN5

Enable input hi-level = 5V

5 EN10

Enable input hi-level = 10V

6 IN1

Input channel 1

7 IN2

Input channel 2

8 IN3

Input channel 3

9 IN4

Input channel 4

10 IN5

Input channel 5

11 IN6

Input channel 6

12 IN7

Input channel 7

13 IN8

Input channel 8

14 NOK

Output inverted status

15 ENFS Enable input full scale hi-level = VB

16 GNDR Ground (R)

17 GND

Ground

18 OUT8 Output channel 8

19 OUT7 Output channel 7

20 OUT6 Output channel 6

21 OUT5 Output channel 5

22 OUT4 Output channel 4

23 OUT3 Output channel 3

24 OUT2 Output channel 2

TP

TP Thermal-Pad

The Thermal Pad is to be connected to a ground plane on the PCB. Connections between GND, GNDR

and the ground plane should be conciled to system FMEA aspects.