FX929AD2 datasheet(35/44 Pages) CMLMICRO

35 / 44 page

4-Level FSK Modem Data Pump

FX929A

D/929A/4

1.6.3

Clock Extraction and Level Measurement Systems

The FX929A is intended for use in systems where:

The Symbol Sync pattern is transmitted immediately on start-up of the transmitter, before the first

Frame Sync pattern (see Figure 17).

A Base Station may remain powered up indefinitely, transmitting concatenated Frames without

intervening Symbol Sync patterns (each Frame starting with the Frame Synch pattern and symbol

timing being maintained from one Frame to the next).

A receiving modem may be switched onto a channel before the distant transmitter has started up, or

may be switched onto a channel where the transmitting station is already sending concatenated

Frames.

Whenever the receiving modem is enabled or switched onto a channel it needs to establish the received

symbol levels and timing and look for a Frame Sync pattern in the incoming signal. This is best done by the

following procedure.

Ensure that the Control Register's PLLBW bits are set to 'Wide' and the LEVRES bits to 'Slow Peak

Detect'.

Wait until a received carrier has been present for 8 symbol times. This 8-symbol delay gives time for

the received signal to propagate through the modem's RRC filter and can usefully be included in the

radio's carrier detect circuitry.

Write a SFS or SFP task to the Command Register with the AQSC and AQLEV bits set to '1'.

When the modem interrupts to signal that it has recognised a Frame Sync pattern (or completed the

SFP task) then change the PLLBW bits to 'Medium'.

Once the receiving modem has achieved level and symbol timing synchronisation with a particular channel - as

evidenced by recognition of a Frame Sync pattern - then subsequent concatentated Frames can be read by

simply issuing SFS or SFP tasks at appropriate times, keeping the ASQSC and AQLEV bits at zero, and the

PLLLBW and LEVRES bits at their current 'Medium' and 'Slow Peak Detect' settings.

Received signal

from FM discriminator

to Modem :

Set AQSC and AQLEV bits

to start acquisition sequences :

Symbol Sync

Frame Sync

rest of frame

noise

Level Measurement and

Clock Extraction circuits :

8-symbol delay

Increasing accuracy and lengthening response times

Figure 17 Acquisition Sequence Timing (Transmitter Power-Up)

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