FX929AD2 datasheet(24/44 Pages) CMLMICRO

24 / 44 page

4-Level FSK Modem Data Pump

FX929A

D/929A/4

Mode Register B7: IRQNEN - IRQN Output Enable

When this bit is set to '1', the IRQN chip output pin is pulled low (to Vss) whenever the IRQ bit of the Status

Mode Register B6: INVSYM - Invert Symbols

This bit controls the polarity of the transmitted and received symbol voltages.

Symbol

Signal at TXOP

Signal at RXFB

'+3'

Above VBIAS

Below VBIAS

'-3'

Below VBIAS

Above VBIAS

'+3'

Below VBIAS

Above VBIAS

'-3'

Above VBIAS

Below VBIAS

Mode Register B5: TXRXN - Tx/Rx Mode

Setting this bit to '1' puts the modem into Transmit mode, clearing it to '0' puts the modem into Receive mode.

Note that changing between receive and transmit modes will cancel any current task.

Mode Register B4: RXEYE - Show Rx Eye

This bit should normally be set to '0'.

Setting it to '1' when the modem is in receive mode configures the modem into a special test mode, in which the

input of the Tx o/p buffer is connected to the Rx Symbol/Clock extraction circuit at a point which carries the

equalised receive signal. This may be monitored with an oscilloscope (at the TXOP pin itself), to assess the

quality of the complete radio channel including the Tx and Rx modem filters, the Tx modulator and the Rx IF

filters and FM demodulator.

The resulting eye diagram (for reasonably random data) should ideally be as shown in Figure 13, with 4 'crisp'

and equally spaced crossing points.

Figure 13 Ideal 'RXEYE' Signal

Mode Register B3: PSAVE - Powersave

When this bit is a '1', the modem will be in a 'powersave' mode in which the internal filters, the Rx Symbol and

Clock extraction circuits and the Tx o/p buffer will be disabled, and the TxOp pin will be connected to Vbias

through a high value resistance.

The Xtal Clock oscillator, Rx i/p amplifier and the µC interface logic will

continue to operate.

FX929AD2 Datasheet(PDF) 24 Page - CML Microcircuits