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LC4101C Datasheet(PDF) 2 Page - Sanyo Semicon Device |
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LC4101C Datasheet(HTML) 2 Page - Sanyo Semicon Device |
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2 / 9 page ![]() Allowable Operating Ranges at Ta = –20 to +75°C, standard VSS, VEEn = VEE1 or VEE2, VSSn = VSS1 or VSS2 Note: 1. The voltages V0, V2, V3, and V5 must obey the relationships VEEn ≥ V0 ≥ V2 ≥ VEE – 7, and 7 ≥ V3 ≥ V5 ≥ VSSn. (Unit: V) 2. When turning on the power supplies, first turn on the logic system power supply and then turn on the high-voltage system power supply; alternatively, turn both on at the same time. When turning off the power supplies, first turn off the high-voltage system power supply and then turn off the logic system power supply; alternatively, turn both off at the same time. No. 5280-2/9 LC4101C Parameter Symbol Conditions min typ max Unit VDD 3.0 5.5 V Supply voltage VEEn 20 36 V VSSn 0 V Input high-level voltage VIH D0 to D7, CP, L/R, BS, DF, TEST, DISP, 0.8 VDD VDD V EIO1, EIO2, LOAD Input low-level voltage VIL D0 to D7, CP, L/R, BS, DF, TEST, DISP, 0 0.2 VDD V EIO1, EIO2, LOAD V0, V2 V0, V2 VEEn – 7 VEEn V Input voltage V3 V3 0 VSSn + 7 V V5 V5 0 V CP clock frequency fcp CP 12 MHz High-level load tw (ldh) LOAD 50 ns pulse width High-level clock tw (cph) CP 28 ns pulse width Low-level clock tw (cpl) CP 28 ns VDD = pulse width 5 V ± 10% Load clock frequency fload LOAD 1 MHz LOAD/CP setup time tsu (ld) LOAD, CP 30 ns LOAD/CP hold time tho (ld) LOAD, CP 200 ns DATA/CP setup time tsu (cp) CP, D0 to D7 28 ns DATA/CP hold time tho (cp) CP, D0 to D7 20 ns EIO input setup time tsu (ei) CP, EIO1, EIO2 30 ns Clock rise time tr LOAD, CP 50 ns Clock fall time tf LOAD, CP 50 ns CP clock frequency fcp CP 6.5 MHz High-level load tw (ldh) LOAD 50 ns pulse width High-level clock tw (cph) CP 40 ns pulse width Low-level clock tw (cpl) CP 40 ns VDD = pulse width 3 to 4.5 V Load clock frequency fload LOAD 200 kHz LOAD/CP setup time tsu (ld) LOAD, CP 35 ns LOAD/CP hold time tho (ld) LOAD, CP 350 ns DATA/CP setup time tsu (cp) CP, D0 to D7 50 ns DATA/CP hold time tho (cp) CP, D0 to D7 50 ns EIO input setup time tsu (ei) CP, EIO1, EIO2 45 ns Clock rise time tr LOAD, CP 50 ns Clock fall time tf LOAD, CP 50 ns |
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