Switching Characteristics

Note: 1. Since this IC detects the EIO inputs on the rising edge of the CP signal, the EIO inputs must be set up before the first data is input. As a result, a

tho(ld) clock stop period is required directly after the rise of the LOAD signal if the clock frequency is relatively high.

Note: 2. If this IC is used with a 4-bit width data input, the number of data clocks between one LOAD and the next LOAD must be doubled.

No. 5280-4/9

LC4101C

Parameter

Symbol

Conditions

min

typ

max

Unit

EIO output delay time

30 pF capacitive load

39

ns

LD/EIO output delay time

30 pF capacitive load

70

ns

LOAD-OUTn delay time

100 pF capacitive load

700

µs

DF-OUTn delay time

100 pF capacitive load

1.4

µs

Parameter

Symbol

Conditions

min

typ

max

Unit

EIO output delay time

30 pF capacitive load

80

ns

LD/EIO output delay time

30 pF capacitive load

130

ns

LOAD-OUTn delay time

100 pF capacitive load

3

µs

DF-OUTn delay time

100 pF capacitive load

3

µs