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LC651154N Datasheet(PDF) 31 Page - Sanyo Semicon Device |
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LC651154N Datasheet(HTML) 31 Page - Sanyo Semicon Device |
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31 / 39 page  Parameter Symbol Conditions Applicable pins and notes Ratings Unit min typ max Oscillator characteristics • Figure 3, fo = 400 kHz OSC1, OSC2 392 400 408 Ceramic oscillator • Figure 3, fo = 800 kHz OSC1, OSC2 784 800 816 Oscillator frequency fCFOSC*7 • Figure 3, fo = 1 MHz OSC1, OSC2 980 1000 1020 kHz • Figure 3, fo = 4 MHz, with the OSC1, OSC2 3920 4000 4080 divide-by-four circuit used. • Figure 4, fo = 400 kHz 10 Oscillator stabilization time *8 tCFS • Figure 4, fo = 800 kHz, 1 MHz, or 10 ms 4 MHz, with the divide-by-four circuit used. Two-pin RC oscillator fMOSC • Figure 2, Cext = 270 pF ±5% OSC1, OSC2 290 400 841 kHz Oscillator frequency • Figure 2, Rext = 5.6 k Ω ±1% Pull-up resistor RPP • Output n-channel transistors off Pull-up resistor 814 30 I/O ports • VIN = VSS, VDD = 5 V specification ports k Ω RES Ru VIN = VSS, VDD = 5 V RES 200 500 800 External reset characteristics tRST See figure 5. Reset time • f = 1 MHz Pin capacitances Cp • With all pins other than the pin 10 pF being tested at VIN = VSS. Serial clock Input clock cycle time tCKCY (1) Figure 6 SCK 2.0 Output clock cycle time tCKCY (2) Figure 6 SCK 64 × TCYC*9 Input clock low-level pulse tCKL (1) Figure 6 SCK 2.0 width Output clock low-level pulse tCKL (2) Figure 6 SCK 32 × TCYC width Input clock high-level pulse tCKH (1) Figure 6 SCK 2.0 width Output clock high-level tCKH (2) Figure 6 SCK 32 × TCYC pulse width Serial input Data setup time tICK SI 0.5 µs Data hold time tCKI SI 0.5 Serial output • Stipulated with respect to the falling edge of SCK. • With an external resistor of 1 k Ω SO 1.0 Output delay time tCKO and an external capacitor of 50 pF on only the n-channel open-drain pins. • Figure 6 Pulse output function Period tPCY PE0 64 × TCYC High-level pulse width tPH PE0 32 × TCYC ±10% Low-level pulse width tPL PE0 32 × TCYC ±10% • Stipulated with respect to the rising edge of SCK. • Figure 6 No. 6278-31/39 LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L Continued from preceding page. Continued on next page. • Figure 7 • TCYC = 4 × system clock period • With an external resistor of 1 k Ω and an external capacitor of 50 pF on only the n-channel open-drain pins. |
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