65C datasheet(105/112 Pages) RENESAS

105 / 112 page

R01DS0015EJ0100 Rev.1.00

Page 105 of 109

Feb 07, 2011

M16C/65C Group

5. Electrical Characteristics

Figure 5.33

Timing Diagram

Read timing

Write timing

BCLK

CSi

ALE

DBi

ADi

BHE

WR, WRL

WRH

BCLK

CSi

ALE

DBi

ADi

BHE

tcyc

td(BCLK-CS)

30ns(max.)

td(BCLK-AD)

30ns(max.)

td(BCLK-ALE)

25ns(max.)

th(BCLK-ALE)

-4ns(min.)

td(BCLK-RD)

30ns(max.)

Hi-Z

tsu(DB-RD)

Hi-Z

td(BCLK-CS)

30ns(max.)

td(BCLK-AD)

30ns(max.)

td(BCLK-ALE)

25ns(max.)

td(BCLK-WR)

30ns(max.)

(0.5 × t

-15)ns(min.)

cyc

tac4(RD-DB)

(n × t

-60)ns(max.)

cyc

= V

= 3V

CC1

CC2

Memory Expansion Mode, Microprocessor Mode

(in wait state setting 2

φ + 3 φ, 2 φ + 4 φ, 3φ + 4 φ, and 4 φ + 5 φ, and

when accessing external area)

n: 3 (when 2

φ + 3 φ)

4 (when 2

φ + 4 φ or 3 φ + 4 φ)

5 (when 4

φ + 5 φ)

th(BCLK-AD)

0ns(min.)

th(BCLK-CS)

0ns(min.)

th(RD-AD)

0ns(min.)

th(BCLK-RD)

0ns(min.)

th(RD-DB)

0ns(min.)

th(BCLK-CS)

0ns(min.)

th(BCLK-AD)

0ns(min.)

th(BCLK-ALE)

-4ns(min.)

th(WR-AD)

th(BCLK-WR)

0ns(min.)

td(DB-WR)

{(n-0.5) × t

-40}ns(min.)

cyc

th(WR-DB)

(0.5 × t

-25)ns(min.)

cyc

Measuring conditions

= V

= 3V

CC1

CC2

Input timing voltage: V = 0.6 V, V

= 2.4 V

Output timing voltage: V

= 1.5 V, V

= 1.5 V

tcyc =

f(BCLK)

tcyc

td(BCLK-DB)

40ns(max.)

60ns(min.)

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