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MIC2199BML Datasheet(PDF) 7 Page - Micrel Semiconductor

Part # MIC2199BML
Description  300kHz 4mm4mm Synchronous Buck Converter
PDF  14 Pages
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

MIC2199BML Datasheet(HTML) 7 Page - Micrel Semiconductor

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Micrel, Inc.
MIC2199.
January 2010
7
M9999-011310
Current Limit
The MIC2199 output current is detected by the voltage drop
across the external current-sense resistor (RCS in Figure
2.). The current limit threshold is 75mV±20mV. The current-
sense resistor must be sized using the minimum current
limit threshold. The external components must be designed
to withstand the maximum current limit. The current-sense
resistor value is calculated by the equation below:
R
55mV
I
CS
OUT(max)
=
The maximum output current is:
I
95mV
R
OUT(max)
CS
=
Thecurrent-sensepinsCSH(pin4)andVOUT (pin 5) are
noise sensitive due to the low signal level and high input im-
pedance.ThePCBtracesshouldbeshortandroutedclose
to each other. A small (1nF to 0.1µF) capacitor across the
pins will attenuate high frequency switching noise.
When the peak inductor current exceeds the current limit
threshold, the current limit comparator, in Figure 2, turns off
thehigh-sideMOSFETfortheremainderofthecycle.The
output voltage drops as additional load current is pulled from
theconverter.Whentheoutputvoltagereachesapproximately
0.4V, the circuit enters frequency-foldback mode and the
oscillator frequency will drop to 75kHz while maintaining the
peak inductor current equal to the nominal 75mV across the
externalcurrent-senseresistor.Thislimitsthemaximumoutput
power delivered to the load under a short circuit condition.
Reference, Enable and UVLO Circuits
The output drivers are enabled when the following conditions
aresatisfied:
• TheVDD voltage (pin 7) is greater than its under-
voltage threshold (typically 4.25V).
• Thevoltageontheenablepinisgreaterthanthe
enable UVLO threshold (typically 2.5V).
The internal bias circuit generates a 0.8V bandgap reference
voltageforthevoltageerroramplifieranda5VVDD voltage
forthegatedrivecircuit.TheMIC2199usesFB(pin3)for
output voltage sensing.
The enable pin (pin 2) has two threshold levels, allowing
the MIC2199 to shut down in a low current mode, or turn off
output switching in UVLO mode. An enable pin voltage lower
than the shutdown threshold turns off all the internal circuitry
and reduces the input current to typically 0.1µA.
If the enable pin voltage is between the shutdown and UVLO
thresholds, the internal bias, VDD,andreferencevoltagesare
turned on. The output drivers are inhibited from switching and
remain in a low state. Raising the enable voltage above the
UVLO threshold of 2.5V enables the output drivers.
EitheroftwoUVLOconditionswilldisabletheMIC2199from
switching.
• WhentheVDD drops below 4.1V
• Whentheenablepindropsbelowthe2.5Vthreshold
MOSFET Gate Drive
The MIC2199 high-side drive circuit is designed to switch
anN-ChannelMOSFET.Referringtotheblockdiagramin
Figure 2, a bootstrap circuit, consisting of D2 and CBST, sup-
plies energy to the high-side drive circuit. Capacitor CBST is
chargedwhilethelow-sideMOSFETisonandthevoltageon
the VSW pin (pin 11) is approximately 0V. When the high-side
MOSFETdriveristurnedon,energyfromCBST is used to
turntheMOSFETon.AstheMOSFETturnson,thevoltage
on the VSW pin increases to approximately VIN. Diode D2
is reversed biased and CBSTfloatshighwhilecontinuingto
keepthehigh-sideMOSFETon.Whenthelow-sideswitch
is turned back on, CBST is recharged through D2.
The drive voltage is derived from the internal 5V VDD bias
supply. The nominal low-side gate drive voltage is 5V and
the nominal high-side gate drive voltage is approximately
4.5VduethevoltagedropacrossD2.Afixed80nsdelay
between the high- and low-side driver transitions is used
topreventcurrentfromsimultaneouslyflowingunimpeded
throughbothMOSFETs.
Oscillator
The internal oscillator is free running and requires no external
components. The nominal oscillator frequency is 500kHz. If
the output voltage is below approximately 0.4V, the oscillator
operates in a frequency-foldback mode and the switching
frequency is reduced to 75kHz.
TIME
fS = 75kHz
VOUT = 0.4V
fS = 300kHz
VIN = 7V
VOUT = 3.3V
Figure 4. Startup Waveform
Above 0.4V, the switching frequency increases to 500kHz
causing the output voltage to rise a greater rate. The rise
time of the output is dependent on the output capacitance,
output voltage, and load current. The oscilloscope photo in
Figure 4 show the output voltage at startup.



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