MIC2267YML datasheet(10/19 Pages) MICREL

10 / 19 page

Micrel Inc.

MIC2267

January 2011

M9999-011711-A

This is, effectively, cycle by cycle input current limit

where the average input current in each cycle is limited.

The advantage of this scheme is that when the input

current budget has been used up for that cycle and the

top switch goes off, the output can still draw current from

ground and switching continues in an efficient manor.

Conventional input current limit schemes which utilize an

input switch will effectively drop VIN and leave the

switcher at 100% duty cycle; in effect current limiting like

an LDO current limits.

FILTER

The filter pin can be used to implement a delay to the

input current limit, thus allowing acceptable bursts of

current to pass, unaffected. However the magnitude of

the over current will act to shorten the allowable pulse

width; effectively regulating charge passed; thus for a

given input capacitor, the droop during over current

peaks can be kept constant.

The Delay circuit is an identical circuit to the LIMIT circuit

except that the current being stored on the integrating

capacitor is first sent through a single pole RC filter i.e. a

replica of the P-Channel Drain current is fed into a

parallel RC. The R is set internally to 50kΩ (

±20%) and

the C is the external (CFILTER). The FILTER current limit

is set to 80% of the nominal input current limit, i.e., in the

previous example, whereas the LIMIT circuit has to

charge the storage capacitor CINT to 1V, the FILTER

current limit circuit only has to charge the integration

storage capacitor CINTFIL to 0.8V.

Figure 2. MIC2267 FILTER Pin Operation

The rising function after the integration block (voltage on

CINTFIL) is actually discharged to 0v each cycle, but for

clarity, it is shown as an ‘envelope’ to show its rising

characteristic.

FILTER

LIM

DELAY

50kΩ

0.8

⎟

⎠

⎞

⎜

⎝

⎛

−

Typically, CINTFIL takes time to reach this 80% trip level.

Therefore, asserting current limit on the current cycle is

highly dependant on internal delays and the extremity of

the over current. Therefore, if the filter circuit reaches the

80% trigger level in a given cycle (n), the actual current

limit is allowed to work during the next cycle (n+1).

When VOUT < 90% VOUT nominal, e.g. during startup or

large load transients, the filter/delay function is disabled.

This is to allow a defined startup current limit and reduce

voltage peaks.

ENABLE (EN)

This is the enable pin. Taking this pin above 1.8V will

enable the part to begin switching. Taking this pin below

0.4V will put the part into the shutdown mode where

nominally, the part will consume < 1µA.

POWER GOOD (PGOOD)

This is an open drain output which can be connected via

a pull up resistor to VOUT or an external voltage up to

5.5V. This pin is pulled low while the part is enabled and

the output is below 90% of the nominal output voltage.

When the trigger threshold of nominally >90% nominal

VOUT is crossed, the PGOOD N-Channel FET is switched

off and the pin will be high impedance.

Note that the power good function is inactive while the

part is in shutdown (EN=Low). I.E. If the PG pull up

resistor is connected to VIN, PG will be high when EN is

below the enable threshold.

COMP

COMP is the output connection of the voltage error

transconductance amplifier. The MIC2267 is a current

mode controller and therefore will require just a capacitor

and resistor connected from COMP to AGND to create a

single pole, single zero compensator to stabilize the

loop. An additional capacitor from COMP to AGND can

be added to reduce switching jitter due to high frequency

switching noise entering the loop.

If desirable, slope compensation can be increased/

reduced to improve stability/transient response over a

wide duty cycle range including 100%. In such cases,

additional compensation may be added to this pin if

required.

Connect this pin to the junction of the output voltage

feedback resistors. The regulation loop will set the

output voltage to the correct level determined by these

feedback resistor values. The output voltage will be:

VOUT = VREF(1+R1/R2)

For most applications, R2 can be set to 10k and R1 can

be found by:

R1 = R2(VOUT/VREF – 1)

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