LC66P516 datasheet(13/25 Pages) SANYO

13 / 25 page

Electrical Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 5.5 V unless otherwise specified.

No. 5483-13/25

LC662304A, 662306A, 662308A, 662312A, 662316A

Parameter

Symbol

Conditions

min

typ

max

Unit

Note

P2, P3 (except for the P33/HOLD pin),

IIH1

P61, and P63: VIN = 10.0 V, with the output

5.0

µA

Nch transistor off

P0, P1, P4, P5, P6, PC, OSC1, RES, and

Input high-level current

IIH2

P33/HOLD (Does not apply to PD, PE, PC2,

1.0

µA

PC3, P61, and P63.): VIN = VDD,

with the output Nch transistor off

IIH3

PD, PE, PC2, PC3: VIN = VDD,

1.0

µA

with the output Nch transistor off

IIL1

Input ports other than PD, PE, PC2, and PC3:

–1.0

µA

Input low-level current

VIN = VSS, with the output Nch transistor off

IIL2

PC2, PC3, PD, PE: VIN = VSS,

–1.0

µA

with the output Nch transistor off

P2, P3 (except for the P33/HOLD pin),

VDD – 1.0

Output high-level voltage

VOH1

P6, and PC: IOH = –1 mA

P2, P3 (except for the P33/HOLD pin),

VDD – 0.5

P6, and PC: IOH = –0.1 mA

Value of the output pull-up resistor

RPO

P0, P1, P4, P5

100

150

kΩ

VOL1

P0, P1, P2, P3, P4, P5, P6, and PC

0.4

Output low-level voltage

(except for the P33/HOLD pin): IOL = 1.6 mA

VOL2

P0, P1, P2, P3, P4, P5, P6, and PC

1.5

(except for the P33/HOLD pin): IOL = 8 mA

IOFF1

P2, P3, P61, P63: VIN = VDD

5.0

µA

Output off leakage current

IOFF2

Does not apply to P2, P3, P61, and P63:

1.0

µA

VIN = VDD

[Schmitt characteristics]

Hysteresis voltage

VHYS

0.1 VDD

High-level threshold voltage

Vt H

P2, P3, P5, P6, OSC1 (EXT), RES

0.5 VDD

0.8 VDD

Low-level threshold voltage

Vt L

0.2 VDD

0.5 VDD

[Ceramic oscillator]

Oscillator frequency

fCF

OSC1, OSC2: Figure 2, 4 MHz

4.0

MHz

Oscillator stabilization time

fCFS

Figure 3, 4 MHz

10.0

[Serial clock]

Cycle time

Input

tCKCY

0.9

µs

Output

2.0

Tcyc

Low-level and high-level

Input

tCKL

0.4

µs

pulse widths

Output

tCKH

1.0

Tcyc

Rise an fall times

Output

tCKR, tCKF

0.1

µs

[Serial input]

Data setup time

tICK

0.3

µs

Data hold time

tCKI

0.3

µs

[Serial output]

SO0: With the timing of Figure 4 and the test

Output delay time

tCKO

load of Figure 5. Stipulated with respect to the

0.3

µs

falling edge (

↓) of SCK0.

SI0: With the timing of Figure 4.

Stipulated with respect to the rising edge (

↑) of

SCK0.

SCK0: With the timing of Figure 4 and the test

load of Figure 5.

Continued on next page.

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