MIC22601 datasheet(9/18 Pages) MICREL

9 / 18 page

Micrel, Inc.

MIC22601

May 2009

M9999-050509-A

Functional Description

PVIN

PVIN is the input supply to the internal 30m

Ω P Channel

Power MOSFET. This should be connected externally to

the SVIN pin. The supply voltage range is from 2.6V to

5.5V. A 10µF ceramic is recommended for bypassing

each PVIN supply.

EN/DLY

This pin is internally fed with a 1µA current source to VIN.

A delayed turn on is implemented by adding a capacitor

to this pin. The delay is proportional to the capacitor

value. The internal circuits are held off until EN/DLY

reaches the enable threshold of 1.24V.

RC allows the slew rate of the output voltage to be

programmed by the addition of a capacitor from RC-to-

ground. RC is internally fed with a 1µA current source

and VOUT slew rate is proportional to the capacitor and

the 1µA source.

Delay

Adding a capacitor to this pin allows the delay of the

POR signal.

When VOUT reaches 90% of its nominal voltage, the

Delay pin current source (1µA) starts to charge the

external capacitor. At 1.24V, POR is asserted high.

Comp

The MIC22601 uses an internal compensation network

containing a fixed frequency zero (phase lead response)

and pole (phase lag response) which allows the external

compensation network to be much simplified for stability.

The addition of a single capacitor and resistor will add

the necessary pole and zero for voltage mode loop

stability when using low value, low ESR ceramic

capacitors.

The feedback pin provides a control path to control the

output. A resistor divider connecting the feedback to the

output is used to adjust the desired output voltage. Refer

to the feedback section in the “Applications Information”

for more detail.

POR

This is an open drain output. A 47k resistor can be used

for a pull up to this pin. POR is asserted high when

output voltage reaches 90% of nominal set voltage and

after the delay set by CDELAY. POR is asserted low

without delay when enable is set low or when the output

goes below the -10% threshold. For a Power Good (PG)

function, the delay can be set to a minimum. This can be

done by removing the Delay capacitor.

This is the connection to the source of the internal P-

Channel MOSFET and drain of the N-Channel MOSFET.

This is a high frequency high power connection;

therefore traces should be kept as short and as wide as

practical. In order to achieve the highest efficiency and

reduce internal losses, connect a Schottky diode directly

from this pin-to-ground as close to the package as

possible.

SGND

Internal signal ground for all low power sections.

PGND

Internal ground connection to the source of the internal

N-Channel MOSFETs.

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