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LT3688

3688f

Output Voltage Monitoring

The LT3688 provides power supply monitoring for

microprocessor-based systems. The features include

power-on reset (POR) and watchdog timing.

A precise internal voltage reference and glitch immune

precision POR comparator circuits monitor the LT3688

output voltages. Each channel’s output voltage must be

above 90% of the programmed value for RST not to be

asserted (refer to the Timing Diagram). The LT3688 will

assert RST during power-up, power-down and brownout

conditions. Once the output voltage rises above the RST

threshold, the adjustable reset timer is started and RST is

released after the reset timeout period. On power-down,

once the output voltage drops below RST threshold, RST

is held at a logic low. The reset timer is adjustable using

external capacitors. This capability helps hold the micro-

processor in a stable shutdown condition. The RST pin

has weak pull-up to the BIAS pin.

The above discussion is concerned only with the DC

value of the monitored supply. Real supplies also have

relatively high-frequency variation, from sources such as

load transients, noise, and pickup. These variations should

not be considered by the monitor in determining whether

a supply voltage is valid or not. The variations may cause

spurious outputs at RST, particularly if the supply voltage

is near its trip threshold.

Two techniques are used to combat spurious reset without

sacriﬁcing threshold accuracy. First, the timeout period

helps prevent high-frequency variation whose frequency is

above 1/ tRST from appearing at the RST output. When the

voltage at FB goes below the threshold, the RST pin asserts

low. When the supply recovers past the threshold, the reset

timer starts (assuming it is not disabled), and RST does not

go high until it ﬁnishes. If the supply becomes invalid any

time during the timeout period, the timer resets and starts

fresh when the supply next becomes valid. While the reset

timeout is useful for preventing toggling of the reset output

in most cases, it is not effective at preventing nuisance

resets due to short glitches (due to load transients or other

effects) on a valid supply. To reduce sensitivity to these

short glitches, the comparator has additional anti-glitch

circuitry. Any transient at the input of the comparator needs

to be of sufﬁcient magnitude and duration (tUV) before it

can change the monitor state. The combination of the reset

timeout and anti-glitch circuitry prevents spurious changes

in output state without sacriﬁcing threshold accuracy.

Watchdog Timer

The LT3688 includes an adjustable watchdog timer that

monitors a μP’s activity. If a code execution error occurs

in a μP, the watchdog will detect this error and will set the

WDO low. This signal can be used to interrupt a routine

or to reset a μP.

The watchdog circuitry is triggered by negative edges on

the WDI pin. The window mode restricts the WDI pin’s

negative going pulses to appear inside a programmed

time window (see the Timing Diagram) to prevent WDO

from going low. If more than two pulses are registered

in the window’s fast period, the WDO is forced to go low.

The WDO also goes low if no negative edge is supplied

to the WDI pin in the window’s slow timer period. During

a code execution error, the microprocessor will output

WDI pulses that would be either too fast or too slow. This

condition will assert WDO and force the microprocessor

to reset the program. In window mode, the WDI signal

frequency is bounded by an upper and lower limit for

normal operation. The WDI input frequency period should

be higher than the window mode’s fast period and lower

than the window mode’s slow period to keep WDO high

under normal conditions. The window mode’s fast and slow

times have a ﬁxed ratio of 16 between them. These times

can be increased or decreased by adjusting an external

capacitor on the CWDT pin.

When WDO is asserted, a timer is enabled for a time

equivalent to 1/8th of the watchdog window upper

boundary. Any WDI pulses that appear while the reset

timer is running are ignored. When the timer expires, the

WDO is allowed to go high again. Therefore, if no input

is applied to the WDI pin, then the watchdog circuitry

produces a train of pulses on the WDO pin. The high

time of this pulse train is equal to the watchdog window

upper boundary, and low time is equal to the 1/8th of the

watchdog window upper boundary.

APPLICATIONS INFORMATION

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