Device Description

The device is a PFM flyback dc-dc boost converter,

working in discontinuous mode.

With reference to the chip block diagram and typical

application circuit, the operation of the device is as

follows:

Control loop

When ‘EN’ is high, the control circuits become active

and the low side of the coil (L1) is switched to ground

via NDMOS transistor (MN). The current in L1 is

allowed to build up to an internally defined level

(nominally 320mA) before MN is turned off. The energy

stored in L1 is then transferred to the output capacitor

(C2) via Schottky diode (D1). The output voltage is

(which may be shunted externally at pin ‘FB’) and

nominal). A comparator senses when the output

voltage is above that set by the reference and its output

is used to control the ‘off’ time of the output switch. The

control loop is self-oscillating, producing pulses of up

to 5

µs maximum duration (switch ‘on’), at a frequency

that varies in proportion to the output current. The

feedback loop maintains a voltage of VREF at the FB pin

and therefore defines a maximum output voltage equal

output switch is fixed at 0.5

µs nominal, to allow time

for the coil’s energy to be dissipated before the switch

is turned on again. This maintains stable and efficient

operation in discontinuous mode.

Filtered PWM operation

The input of an internal low pass filter is switched to

when the EN pin is low. The output of this filter drives

the comparator within the control loop. A continuous

high state on EN therefore provides a filtered voltage of

value Vref to the comparator. However, by varying the

duty cycle of the EN signal at a suitably high frequency

(f>10kHz), the control loop will see a voltage, that has

an average value equal to the duty cycle multiplied by

voltage to a lower value. It also allows the device to be

both turned on and adjusted with a single signal at the

‘EN’ pin. The output during this mode of operation will

Gated PWM operation

The internal circuitry of the ZXLD1601 is turned off

when no signal is present on the ‘EN’ pin for more than

120

µs (nominal). A low frequency signal applied to the

EN pin will therefore gate the device ‘on’ and ‘off’ at the

gating frequency and the duty cycle of this signal can

*(R1+R2)/R1 x duty cycle. For best accuracy, the gating

frequency should be made as low as possible (e.g.

below 1kHz), such that the turn off delay of the chip is

only a small proportion of the gating period

Further details of setting output current are given in the

application notes.

ZXLD1601

SEMICO NDUC TORS

ISSUE 3 - AUGUST 2004

5