HT68F03 datasheet(77/147 Pages) HOLTEK

77 / 147 page

HT66F03/HT66F04/HT68F03/HT68F04

Rev. 1.30

February 17, 2011

Timer/Counter Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1

Timer/Counter Mode operates in an identical way to the

Compare Match Output Mode generating the same in-

terrupt flags. The exception is that in the Timer/Counter

Mode the TM output pin is not used. Therefore the

above description and Timing Diagrams for the Com-

pare Match Output Mode can be used to understand its

function. As the TM output pin is not used in this mode,

the pin can be used as a normal I/O pin or other

pin-shared function.

PWM Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1

TnIO1 and TnIO0 bits should be set to 10 respectively.

The PWM function within the TM is useful for applica-

tions which require functions such as motor control,

heating control, illumination control etc. By providing a

signal of fixed frequency but of varying duty cycle on the

TM output pin, a square wave AC waveform can be gen-

erated with varying equivalent DC RMS values.

As both the period and duty cycle of the PWM waveform

can be controlled, the choice of generated waveform is

extremely flexible. In the PWM mode, the TnCCLR bit

has no effect as the PWM period. Both of the CCRA and

CCRP registers are used to generate the PWM wave-

form, one register is used to clear the internal counter

and thus control the PWM waveform frequency, while

the other one is used to control the duty cycle. Which

is determined using the TnDPX bit in the TMnC1 regis-

ter. The PWM waveform frequency and duty cycle can

therefore be controlled by the values in the CCRA and

CCRP registers.

An interrupt flag, one for each of the CCRA and CCRP,

will be generated when a compare match occurs from

either Comparator A or Comparator P. The TnOC bit in

the TMnC1 register is used to select the required polar-

ity of the PWM waveform while the two TnIO1 and

TnIO0 bits are used to enable the PWM output or to

force the TM output pin to a fixed high or low level. The

TnPOL bit is used to reverse the polarity of the PWM

output waveform.

Counter Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

(TnOC=1)

Time

Counter cleared

by CCRP

Pause Resume

Counter Stop if

TnON bit low

Counter Reset when

TnON returns high

TnDPX = 0; TnM [1:0] = 10

PWM Duty Cycle

set by CCRA

PWM resumes

operation

Output controlled by

other pin-shared function

Output Inverts

when TnPOL = 1

PWM Period

set by CCRP

TM O/P Pin

(TnOC=0)

PWM Mode -- TnDPX = 0

Note:

1. Here TnDPX=0 -- Counter cleared by CCRP

2. A counter clear sets the PWM Period

3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01

4. The TnCCLR bit has no influence on PWM operation

HT68F03 Datasheet(PDF) 77 Page - Holtek Semiconductor Inc

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