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LTM4600

4600fc

LTM4600 Frequency Adjustment

The LTM4600 is designed to typically operate at 850kHz

across most input and output conditions. The control ar-

chitecture is constant on time valley mode current control.

The fADJ pin is typically left open or decoupled with an

optional 1000pF capacitor. The switching frequency has

been optimized to maintain constant output ripple over the

operating conditions. The equations for setting the operat-

ing frequency are set around a programmable constant on

time. This on time is developed by a programmable current

into an on board 10pF capacitor that establishes a ramp

that is compared to a voltage threshold equal to the output

voltage up to a 2.4V clamp. This ION current is equal to:

ION = (VIN – 0.7V)/110k, with the 110k onboard resistor

from VIN to fADJ. The on time is equal to tON = (VOUT/ION)

• 10pF and tOFF = ts – tON. The frequency is equal to: Freq.

= DC/tON. The ION current is proportional to VIN, and the

regulator duty cycle is inversely proportional to VIN, there-

fore the step-down regulator will remain relatively constant

frequency as the duty cycle adjustment takes place with

lowering VIN. The on time is proportional to VOUT up to a

2.4V clamp. This will hold frequency relatively constant

with different output voltages up to 2.4V. The regulator

switching period is comprised of the on time and off time

as depicted in Figure 17.

Layout Checklist/Example

The high integration of the LTM4600 makes the PCB board

layout very simple and easy. However, to optimize its electri-

cal and thermal performance, some layout considerations

are still necessary.

• Use large PCB copper areas for high current path, in-

cluding VIN, PGND and VOUT. It helps to minimize the

PCB conduction loss and thermal stress

• Place high frequency ceramic input and output capaci-

tors next to the VIN, PGND and VOUT pins to minimize

high frequency noise

• Place a dedicated power ground layer underneath

the unit

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between top layer and other power layers

• Do not put a via directly on pad unless it is capped

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to PGND underneath the unit

Figure 16 gives a good example of the recommended

layout.

Figure 16. Recommended PCB Layout

VIN

PGND

TOP LAYER

VOUT

4600 F16

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