TPS767D301 datasheet(6/158 Pages) TI

6 / 158 page

SM320F28335-HT

SPRS682 – DECEMBER 2010

www.ti.com

6-14

STANDBY Entry and Exit Timing Diagram

.................................................................................. 112

6-15

HALT Wake-Up Using GPIOn

................................................................................................. 114

6-16

PWM Hi-Z Characteristics

..................................................................................................... 115

6-17

ADCSOCAO or ADCSOCBO Timing

........................................................................................ 117

6-18

External Interrupt Timing

....................................................................................................... 117

6-19

SPI Master Mode External Timing (Clock Phase = 0)

..................................................................... 120

6-20

SPI Master Mode External Timing (Clock Phase = 1)

..................................................................... 122

6-21

SPI Slave Mode External Timing (Clock Phase = 0)

....................................................................... 124

6-22

SPI Slave Mode External Timing (Clock Phase = 1)

....................................................................... 125

6-23

Relationship Between XTIMCLK and SYSCLKOUT

....................................................................... 128

6-24

Example Read Access

......................................................................................................... 130

6-25

Example Write Access

......................................................................................................... 131

6-26

Example Read With Synchronous XREADY Access

...................................................................... 133

6-27

Example Read With Asynchronous XREADY Access

..................................................................... 134

6-28

Write With Synchronous XREADY Access

.................................................................................. 136

6-29

Write With Asynchronous XREADY Access

................................................................................ 137

6-30

External Interface Hold Waveform

............................................................................................ 139

6-31

XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)

.................................................. 140

6-32

ADC Power-Up Control Bit Timing

........................................................................................... 142

6-33

ADC Analog Input Impedance Model

........................................................................................ 143

6-34

Sequential Sampling Mode (Single-Channel) Timing

...................................................................... 144

6-35

Simultaneous Sampling Mode Timing

....................................................................................... 145

6-36

McBSP Receive Timing

........................................................................................................ 149

6-37

McBSP Transmit Timing

....................................................................................................... 149

6-38

McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

................................................... 150

6-39

McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

................................................... 151

6-40

McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

................................................... 152

6-41

McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

................................................... 153

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