TPS767D301 datasheet(65/158 Pages) TI

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ResultRegisters

EPWMSOCB

S/W

GPIO/

XINT2_ADCSOC

EPWMSOCA

S/W

Sequencer2

Sequencer1

SOC

ADCControlRegisters

70B7h

70B0h

70AFh

70A8h

ResultReg15

ResultReg8

ResultReg7

ResultReg1

ResultReg0

12-Bit

ADC

Module

Analog

MUX

ADCINA0

ADCINA7

ADCINB0

ADCINB7

System

ControlBlock

High-Speed

Prescaler

HSPCLK

ADCENCLK

DSP

SYSCLKOUT

S/H

HALT

SM320F28335-HT

www.ti.com

SPRS682 – DECEMBER 2010

Figure 4-8. Block Diagram of the ADC Module

To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent

possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths.

This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs.

Furthermore, proper isolation techniques must be used to isolate the ADC module power pins ( VDD1A18,

VDD2A18 , VDDA2, VDDAIO) from the digital supply.Figure 4-9 shows the ADC pin connections for the devices.

NOTE

1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the

ADC module is controlled by the high-speed peripheral clock (HSPCLK).

2. The behavior of the ADC module based on the state of the ADCENCLK and HALT

signals is as follows:

–

ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the

clock to the register will still function. This is necessary to make sure all registers and

modes go into their default reset state. The analog module, however, will be in a low-

power inactive state. As soon as reset goes high, then the clock to the registers will

be disabled. When the user sets the ADCENCLK signal high, then the clocks to the

registers will be enabled and the analog module will be enabled. There will be a

certain time delay (ms range) before the ADC is stable and can be used.

–

HALT: This mode only affects the analog module. It does not affect the registers. In

this mode, the ADC module goes into low-power mode. This mode also will stop the

clock to the CPU, which will stop the HSPCLK; therefore, the ADC register logic will

be turned off indirectly.

Peripherals

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TPS767D301 Datasheet(PDF) 65 Page - Texas Instruments

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