TPS767D301 datasheet(19/158 Pages) TI

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SM320F28335-HT

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SPRS682 – DECEMBER 2010

Table 2-3. Signal Descriptions (continued)

NAME

DESCRIPTION (1)

Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic resonator may be

connected across X1 and X2. The X1 pin is referenced to the 1.9-V core digital power supply. A 1.9-V external

oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to ground. If a 3.3-V

external oscillator is used with the XCLKIN pin, X1 must be tied to GND. (I)

Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and X2. If X2 is not

used it must be left unconnected. (O)

RESET

Device Reset (in) and Watchdog Reset (out).

Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the

location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This

XRS

pin is driven low by the DSC when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the

watchdog reset duration of 512 OSCCLK cycles. (I/OD,

↑)

The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin be driven by an

open-drain device.

ADC SIGNALS

ADCINA7

ADC Group A, Channel 7 input (I)

ADCINA6

ADC Group A, Channel 6 input (I)

ADCINA5

ADC Group A, Channel 5 input (I)

ADCINA4

ADC Group A, Channel 4 input (I)

ADCINA3

ADC Group A, Channel 3 input (I)

ADCINA2

ADC Group A, Channel 2 input (I)

ADCINA1

ADC Group A, Channel 1 input (I)

ADCINA0

ADC Group A, Channel 0 input (I)

ADCINB7

ADC Group B, Channel 7 input (I)

ADCINB6

ADC Group B, Channel 6 input (I)

ADCINB5

ADC Group B, Channel 5 input (I)

ADCINB4

ADC Group B, Channel 4 input (I)

ADCINB3

ADC Group B, Channel 3 input (I)

ADCINB2

ADC Group B, Channel 2 input (I)

ADCINB1

ADC Group B, Channel 1 input (I)

ADCINB0

ADC Group B, Channel 0 input (I)

ADCLO

Low Reference (connect to analog ground) (I)

ADCRESEXT

ADC External Current Bias Resistor. Connect a 22-k

Ω resistor to analog ground.

ADCREFIN

External reference input (I)

Internal Reference Positive Output. Requires a low ESR (50 m

Ω - 1.5 Ω) ceramic bypass capacitor of 2.2 mF to

ADCREFP

analog ground. (O)

Internal Reference Medium Output. Requires a low ESR (50 m

Ω - 1.5 Ω) ceramic bypass capacitor of 2.2 mF to

ADCREFM

analog ground. (O)

CPU AND I/O POWER PINS

VDDA2

ADC Analog Power Pin

VSSA2

ADC Analog Ground Pin

VDDAIO

ADC Analog I/O Power Pin

VSSAIO

ADC Analog I/O Ground Pin

VDD1A18

ADC Analog Power Pin

VSS1AGND

ADC Analog Ground Pin

VDD2A18

ADC Analog Power Pin

VSS2AGND

ADC Analog Ground Pin

VDD

CPU and Logic Digital Power Pin

VDDIO

Digital I/O Power Pin

VSS

Digital Ground Pin

Introduction

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