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MIC2568 Datasheet(PDF) 5 Page - MIC GROUP RECTIFIERS |
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MIC2568 Datasheet(HTML) 5 Page - MIC GROUP RECTIFIERS |
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5 / 10 page ![]() May 2003 5 MIC2568 MIC2568 Micrel Output Timing Diagrams 5V 3.3V 0 0 AB C D VPP OFF VPP OFF VPP to 5V VPP to 3.3V VPP Enable VPP OUT t2 t6 t4 t8 t3 t1 t5 t7 Figure 1. V PP Timing Diagram V PP EN is shown generically. RL = 100Ω. Load capacitance is negligible. Refer to “MIC2568-0 Logic Table” for specific control logic input. At time A)V PP = 3.3V, B)VPP is disabled, C)VPP is programmed to 5V, D)VPP is disabled. AB C D t9 t11 t15 t13 t10 t12 t16 t14 VCC Enable VCC OUT FLAG VCC to 3.3V VCC to 5V VCC OFF VCC OFF 0 5V 3.3V 0 0 Figure 2. V CC Timing Diagram V CC EN is shown generically. RL = 10Ω. Refer to “MIC2568-0 Logic Table” for specific control logic input. At time A)V CC is programmed to 3.3V, B)VCC is disabled, C)VCC is programmed to 5V, D)VCC is disabled. |
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