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IMX53CEC Datasheet(PDF) 188 Page - Freescale Semiconductor, Inc |
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IMX53CEC Datasheet(HTML) 188 Page - Freescale Semiconductor, Inc |
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188 / 204 page  i.MX53xD Applications Processors for Consumer Products, Rev. 2 188 Freescale Semiconductor Package Information and Contact Assignments GPIO_7 AC11 — NVCC_GPIO UHVIO ALT1 gpio1_GPIO[7] Input 360 K Ω PD GPIO_8 AD10 — NVCC_GPIO UHVIO ALT1 gpio1_GPIO[8] Input 360 K Ω PD GPIO_9 AC13 — NVCC_GPIO UHVIO ALT1 gpio1_GPIO[9] Input 100 K Ω PU JTAG_MOD AD15 — NVCC_JTAG GPIO ALT0 sjc_MOD Input 100 K Ω PU JTAG_TCK AD13 — NVCC_JTAG GPIO ALT0 sjc_TCK Input 100 K Ω PD JTAG_TDI AC15 — NVCC_JTAG GPIO ALT0 sjc_TDI Input 47 K Ω PU JTAG_TDO AG15 — NVCC_JTAG GPIO ALT0 sjc_TDO Input Keeper JTAG_TMS AD16 — NVCC_JTAG GPIO ALT0 sjc_TMS Input 47 K Ω PU JTAG_TRSTB AC17 — NVCC_JTAG GPIO ALT0 sjc_TRSTB Input 47 K Ω PU KEY_COL0 AG9 — NVCC_KEYPAD UHVIO ALT1 gpio4_GPIO[6] Input4 100 K Ω PU KEY_COL1 AJ9 — NVCC_KEYPAD UHVIO ALT1 gpio4_GPIO[8] Input 100 K Ω PU KEY_COL2 AG8 — NVCC_KEYPAD UHVIO ALT1 gpio4_GPIO[10] Input 100 K Ω PU KEY_COL3 AJ8 — NVCC_KEYPAD UHVIO ALT1 gpio4_GPIO[12] Input 100 K Ω PU KEY_COL4 AH7 — NVCC_KEYPAD UHVIO ALT1 gpio4_GPIO[14] Input 100 K Ω PU KEY_ROW0 AH9 — NVCC_KEYPAD UHVIO ALT1 gpio4_GPIO[7] Input 360 K Ω PD KEY_ROW1 AH8 — NVCC_KEYPAD UHVIO ALT1 gpio4_GPIO[9] Input 100 K Ω PU KEY_ROW2 AJ7 — NVCC_KEYPAD UHVIO ALT1 gpio4_GPIO[11] Input 100 K Ω PU KEY_ROW3 AG7 — NVCC_KEYPAD UHVIO ALT1 gpio4_GPIO[13] Input 100 K Ω PU KEY_ROW4 AD8 — NVCC_KEYPAD UHVIO ALT1 gpio4_GPIO[15] Input 360 K Ω PD LVDS_BG_RES C18 — NVCC_LVDS_BG ANALOG — LVDS_BG_RES — — LVDS0_CLK_N B19 — NVCC_LVDS LVDS ALT0 gpio7_GPI[25] Input Floating LVDS0_CLK_P A19 — NVCC_LVDS LVDS ALT0 gpio7_GPI[24] Input Floating LVDS0_TX0_N B22 — NVCC_LVDS LVDS ALT0 gpio7_GPI[31] Input Floating LVDS0_TX0_P A22 — NVCC_LVDS LVDS ALT0 gpio7_GPI[30] Input Floating LVDS0_TX1_N A21 — NVCC_LVDS LVDS ALT0 gpio7_GPI[29] Input Floating LVDS0_TX1_P B21 — NVCC_LVDS LVDS ALT0 gpio7_GPI[28] Input Floating LVDS0_TX2_N B20 — NVCC_LVDS LVDS ALT0 gpio7_GPI[27] Input Floating LVDS0_TX2_P A20 — NVCC_LVDS LVDS ALT0 gpio7_GPI[26] Input Floating LVDS0_TX3_N B18 — NVCC_LVDS LVDS ALT0 gpio7_GPI[23] Input Floating LVDS0_TX3_P A18 — NVCC_LVDS LVDS ALT0 gpio7_GPI[22] Input Floating Table 118. PoP 12 x 12 mm Signal Assignments, Power Rails, and I/O (continued) Contact Name Power Rail I/O Buffer Type Out of Reset Condition1 Alt. Mode Function Direct ion Config./ Value |
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