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IMX53CEC Datasheet(PDF) 189 Page - Freescale Semiconductor, Inc |
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IMX53CEC Datasheet(HTML) 189 Page - Freescale Semiconductor, Inc |
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189 / 204 page  Package Information and Contact Assignments i.MX53xD Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 189 LVDS1_CLK_N A15 — NVCC_LVDS LVDS ALT0 gpio6_GPI[27] Input Floating LVDS1_CLK_P B15 — NVCC_LVDS LVDS ALT0 gpio6_GPI[26] Input Floating LVDS1_TX0_N B17 — NVCC_LVDS LVDS ALT0 gpio6_GPI[31] Input Floating LVDS1_TX0_P A17 — NVCC_LVDS LVDS ALT0 gpio6_GPI[30] Input Floating LVDS1_TX1_N A16 — NVCC_LVDS LVDS ALT0 gpio6_GPI[29] Input Floating LVDS1_TX1_P B16 — NVCC_LVDS LVDS ALT0 gpio6_GPI[28] Input Floating LVDS1_TX2_N A14 — NVCC_LVDS LVDS ALT0 gpio6_GPI[25] Input Floating LVDS1_TX2_P B14 — NVCC_LVDS LVDS ALT0 gpio6_GPI[24] Input Floating LVDS1_TX3_N A13 — NVCC_LVDS LVDS ALT0 gpio6_GPI[23] Input Floating LVDS1_TX3_P B13 — NVCC_LVDS LVDS ALT0 gpio6_GPI[22] Input Floating NANDF_ALE N3 L2 NVCC_NANDF UHVIO ALT1 gpio6_GPIO[8] Input 100 K Ω PU NANDF_CLE G16 — NVCC_NANDF UHVIO ALT1 gpio6_GPIO[7] Input 100 K Ω PU NANDF_CS0 P2 M1 NVCC_NANDF UHVIO ALT1 gpio6_GPIO[11] Input 100 K Ω PU NANDF_CS1 A11 — NVCC_NANDF UHVIO ALT1 gpio6_GPIO[14] Input 100 K Ω PU NANDF_CS2 C12 — NVCC_NANDF UHVIO ALT1 gpio6_GPIO[15] Input 100 K Ω PU NANDF_CS3 A12 — NVCC_NANDF UHVIO ALT1 gpio6_GPIO[16] Input 100 K Ω PU NANDF_RB0 C15 — NVCC_NANDF UHVIO ALT1 gpio6_GPIO[10] Input 100 K Ω PU NANDF_RE_B M3 K2 NVCC_EIM_MAIN UHVIO ALT1 gpio6_GPIO[13] Input 100 K Ω PU NANDF_WE_B M2 K1 NVCC_EIM_MAIN UHVIO ALT1 gpio6_GPIO[12] Input 100 K Ω PU NANDF_WP_B T2 N1 NVCC_NANDF UHVIO ALT1 gpio6_GPIO[9] Input 100 K Ω PU PATA_BUFFER_ EN V6 — NVCC_PATA UHVIO ALT1 gpio7_GPIO[1] Input 100 K Ω PU PATA_CS_0 AA2 — NVCC_PATA UHVIO ALT1 gpio7_GPIO[9] Input 100 K Ω PU PATA_CS_1 AB1 — NVCC_PATA UHVIO ALT1 gpio7_GPIO[10] Input 100 K Ω PU PATA_DA_0 N2 L1 NVCC_PATA UHVIO ALT1 gpio7_GPIO[6] Input 100 K Ω PU PATA_DA_1 AB2 — NVCC_PATA UHVIO ALT1 gpio7_GPIO[7] Input 100 K Ω PU PATA_DA_2 Y3 — NVCC_PATA UHVIO ALT1 gpio7_GPIO[8] Input 100 K Ω PU PATA_DATA0 B9 A7 NVCC_PATA UHVIO ALT1 gpio2_GPIO[0] Input 100 K Ω PU PATA_DATA1 B8 B6 NVCC_PATA UHVIO ALT1 gpio2_GPIO[1] Input 100 K Ω PU PATA_DATA10 B10 A8 NVCC_PATA UHVIO ALT1 gpio2_GPIO[10] Input 100 K Ω PU Table 118. PoP 12 x 12 mm Signal Assignments, Power Rails, and I/O (continued) Contact Name Power Rail I/O Buffer Type Out of Reset Condition1 Alt. Mode Function Direct ion Config./ Value |
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