AD6643 datasheet(13/36 Pages) AD

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AD6643

Rev. 0 | Page 13 of 36

CLK+

CLK–

SYNC

DNC

DRVDD

B0/D0– (LSB)

B0/D0+ (LSB)

BD1–/D2–

BD1+/D2+

BD3–/D4–

BD3+/D4+

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE

ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO

GROUND FOR PROPER OPERATION.

PDWN

OEB

CSB

SCLK

SDIO

OR+

OR–

AD9+/D10+ (MSB)

A D9–/D10– (MSB)

AD7+/D8+

A D7–/D8–

DRVDD

AD5+/D6+

A D5–/D6–

AD3+/D4+

A D3–/D4–

AD6643

CHANNEL

MULTIPLEXED

(EVEN/ODD)

LVDS MODE

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

Figure 5. Pin Configuration (Top View), LFCSP Channel Multiplexed (Even/Odd) LVDS

Table 9. Pin Function Descriptions for the Channel Multiplexed (Even/Odd) LVDS Mode

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

10, 19, 28, 37

DRVDD

Supply

Digital Output Driver Supply (1.8 V Nominal).

49, 50, 53, 54, 59,

60, 63, 64

AVDD

Supply

Analog Power Supply (1.8 V Nominal).

4 to 9, 26, 27, 55,

56, 58

DNC

Do Not Connect. Do not connect to these pins.

AGND, Exposed

Paddle

Ground

The exposed thermal paddle on the bottom of the package provides the

analog ground for the part. This exposed paddle must be connected to

ground for proper operation.

ADC Analog

VIN+A

Input

Differential Analog Input Pin (+) for Channel A.

VIN−A

Input

Differential Analog Input Pin (−) for Channel A.

VIN+B

Input

Differential Analog Input Pin (+) for Channel B.

VIN−B

Input

Differential Analog Input Pin (−) for Channel B.

VCM

Output

Common-Mode Level Bias Output for Analog Inputs. This pin should be

decoupled to ground using a 0.1 μF capacitor.

CLK+

Input

ADC Clock Input—True.

CLK−

Input

ADC Clock Input—Complement.

Digital Input

SYNC

Input

Digital Synchronization Pin. Slave mode only.

Digital Outputs

B 0/D0− (LSB)

Output

Channel B LVDS Output 0/Data 0—Complement. The output bit on the rising

edge of the data clock output (DCO) from this output is always a Logic 0.

B 0/D0+ (LSB)

Output

Channel B LVDS Output 0/Data 0—True. The output bit on the rising edge of

the data clock output (DCO) from this output is always a Logic 0.

B D1−/D2−

Output

Channel B LVDS Output Data 1/Data 2—Complement.

B D1+/D2+

Output

Channel B LVDS Output Data 1/Data 2—True.

B D3−/D4−

Output

Channel B LVDS Output Data 3/Data 4—Complement.

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