AD7280ABSTZ datasheet(35/48 Pages) AD

35 / 48 page

AD7280A

Rev. 0 | Page 35 of 48

WRITE ACKNOWLEDGE

For all write commands received by the AD7280A, the device

internally performs a CRC calculation on Bits[D31:D11] of the

received data and verifies this CRC against the CRC transmitted

by the DSP/microprocessor. If there is a difference between the

CRC generated internally and the CRC received from the DSP/

microprocessor, the AD7280A does not perform the write oper-

ation. The AD7280A also checks for the correct position of the

bit pattern 010 in the write command, as described in the Serial

Interface section. If there is a difference between the expected

010 pattern and the pattern received from the DSP/microprocessor,

the AD7280A does not perform the write operation.

If a subsequent 32 SCLK cycle framed by a CS pulse is applied

to the AD7280A, Bit D10 (the write acknowledge bit) on SDO

indicates to the processor whether the last write to the device

was successful (the write acknowledge bit is set if the write was

successful). The write acknowledge bit is included in the 8-bit

CRC on the read cycle. Note that the read register must be loaded

with any value other than 0x00 for the write acknowledge bit to

be correctly passed down the chain of AD7280A devices.

Following is an example of how the write acknowledge bit can

be used when writing to and configuring a stack of AD7280A

devices. This example sets the high byte of the control register

settings on all devices in a stack of eight AD7280As.

Execute a write all command to load the read register with

0x0E (addresses the low byte of the control register).

Execute a write all command to set the high byte of the

control register (Address 0x0D) to the desired values.

Apply an additional eight sets of 32 SCLKs, each framed by

CS, to the master device. The device address bits, D31 to

D27, should be set to 0x1F for each 32 SCLK frame. The

32-bit write command is 0xF800030A. The data read back

from the master device on the first 32 SCLK frame includes

the write acknowledge bit for the control register high byte

write to the master device. The data read back on the

second 32 SCLK frame includes the write acknowledge bit

for the control register high byte write to the first slave

device in the stack, and so on.

To read back the write acknowledge bit from slave AD7280As

in a daisy chain when single registers are being written to,

Bits[D13:D12] of the control register on lower devices in the

chain must be set to 1 (a no-read operation on those devices).

For example, to read back the write acknowledge bit from

Device 1 in the chain after writing to a register on that device,

the read operation of Device 0, the master device, must be turned

off. Also, the SCLK frequency must be lower than 1 MHz when

reading back the write acknowledge bit from devices higher in

the chain than the master device in this mode.

CYCLIC REDUNDANCY CHECK

The AD7280A 32-bit SPI interface includes an 8-bit cyclic

redundancy check (CRC) on the read and write cycles. The CRC

can be used to detect alterations in the data during transmission

to and from the AD7280A. The principle of a cyclic redundancy

check is that the data to be transmitted is divided by a fixed poly-

nomial. The remainder of this mathematical operation is then

attached to the data and forms part of the transmission. At the

receiving end, the same mathematical operation should be com-

pleted on the data received. This operation confirms that the

data received is the same as the data that was originally transmitted.

The polynomial used by the AD7280A to calculate the CRC bits

is x8 + x5 + x3 + x2 + x + 1. This CRC polynomial has a Hamming

distance of 4 for calculations up to 22 bits of data. The division

is implemented using the digital circuit shown in Figure 40.

Write Operation CRC

For writes to the AD7280A, the CRC must be computed in the

DSP/microprocessor and sent as part of the write command.

The CRC must be computed on Bits[D31:D11] of the write

command, that is, the device address, the register address, the

data to be written, the address all parts bit, and Bit D11, which

is a reserved zero input bit. The data is divided by the CRC

polynomial, and the 8-bit remainder, following the division,

becomes the CRC bits, CRC_7 to CRC_0.

If the user is addressing all parts in a stack of AD7280As (by

asserting the address all parts bit, D12), the CRC must be com-

puted using a device address of 0x00, and the data written to the

device must have a device address of 0x00. The AD7280A performs

the same CRC calculation on Bits[D31:D11] of the received data,

and it verifies this CRC against the CRC transmitted by the DSP/

microprocessor. If there is a difference between the CRC gener-

ated within the AD7280A and the CRC received from the DSP/

microprocessor, the AD7280A does not perform the write opera-

tion. To allow the user to verify that the command has been

received and implemented by the AD7280As in the stack, a

write acknowledge bit is also included in the 32-bit read cycles.

For more information about the write acknowledge bit, see the

Write Acknowledge section.

CRC_0

DATA_IN

SCLK

CRC_1

CRC_2

CRC_3

CRC_4

CRC_5

CRC_6

CRC_7

Figure 40. CRC Implementation

AD7280ABSTZ Datasheet(PDF) 35 Page - Analog Devices

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