AD9146BCPZ datasheet(22/52 Pages) AD

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AD9146

Rev. 0 | Page 22 of 52

Name

Address

(Hex)

Bits

Name

Description

Default

Sync Control

0x10

Sync enable

1 = enable the synchronization logic.

Data/FIFO rate toggle

0 = operate the synchronization at the FIFO reset rate.

1 = operate the synchronization at the data rate.

Rising edge sync

0 = sync is initiated on the falling edge of the sync input.

1 = sync is initiated on the rising edge of the sync input.

[2:0]

Sync Averaging[2:0]

Sets the number of input samples that are averaged in

determining the sync phase.

000

000 = 1.

001 = 2.

010 = 4.

011 = 8.

100 = 16.

101 = 32.

110 = 64.

111 = 128.

0x11

[5:0]

Sync Phase Request[5:0]

This register sets the requested clock phase offset after sync.

The offset unit is in DACCLK cycles. This register enables

repositioning of the DAC output with respect to the sync

input. The offset can also be used to skew the DAC outputs

between the synchronized DACs.

000000

000000 = 0 DACCLK cycles.

000001 = 1 DACCLK cycle.

…

111111 = 63 DACCLK cycles.

Sync Status

0x12

Sync lost

1 = synchronization was attained but has been lost.

N/A

Sync locked

1 = synchronization has been attained.

N/A

0x13

[7:0]

Sync Phase Readback[7:0]

Indicates the averaged sync phase offset (6.2 format). If

this value differs from the Sync Phase Request[5:0] value

in Register 0x11, a sync timing error has occurred. For more

information, see the Sync Status Bits section.

N/A

00000000 = 0.0.

00000001 = 0.25.

…

11111110 = 63.50.

11111111 = 63.75.

Data

Receiver

Status

0x15

LVDS FRAME level high

One or both LVDS FRAME input signals have exceeded 1.7 V.

N/A

LVDS FRAME level low

One or both LVDS FRAME input signals have crossed

below 0.7 V.

N/A

LVDS DCI level high

One or both LVDS DCI input signals have exceeded 1.7 V.

N/A

LVDS DCI level low

One or both LVDS DCI input signals have crossed below 0.7 V.

N/A

LVDS data level high

One or more LVDS Dx input signals have exceeded 1.7 V.

N/A

LVDS data level low

One or more LVDS Dx input signals have crossed below 0.7 V.

N/A

DCI Delay

0x16

Delay bypass

0 = enable the on-chip DCI delay feature. Set the delay

using Bits[1:0].

1 = bypass the on-chip DCI delay feature.

[1:0]

DCI Delay[1:0]

These bits control the delay applied to the DCI signal. The DCI

delay affects the sampling interval of the DCI with respect

to the Dx inputs. See Table 14.

00 = 105 ps delay of DCI signal.

01 = 375 ps delay of DCI signal.

10 = 615 ps delay of DCI signal.

11 = 720 ps delay of DCI signal.

AD9146BCPZ Datasheet(PDF) 22 Page - Analog Devices

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