AD9146BCPZ datasheet(30/52 Pages) AD

30 / 52 page

AD9146

Rev. 0 | Page 30 of 52

Bypass DCI Delay Mode

INTERFACE TIMING

An additional option for the timing of the data, DCI, and

FRAME signals requires the DCI to be delayed by 90° ahead

of the data and FRAME signals. In bypass DCI delay mode, the

DCI signal is placed in the optimal data valid window outside

the part, and the delay circuitry inside the part is bypassed. This

mode provides a smaller sampling window that allows for a wider

range of placement area for correct sampling edges. The bypass

DCI delay mode is enabled by setting Bit 2 in Register 0x16 to 1.

The resulting setup and hold times for this mode are as follows:

The timing diagram for the digital interface port is shown in

Figure 37. The sampling point of the data bus nominally occurs

350 ps after each edge of the DCI signal and has an uncertainty

of ±300 ps, as illustrated by the data valid window shown in

Figure 37. The data and FRAME signals must be valid through-

out this window. The data and FRAME signals may change at

any time between data valid windows.

The setup (tS) and hold (tH) times, with respect to the edges,

are shown in Figure 37. The minimum setup and hold times

are shown in Table 14.

•

Minimum setup time (tS): 0.27 ns

•

Minimum hold time (tH): 0.09 ns

DCI

DATA

tDATA

DATA VALID

WINDOW

•

Sampling interval: 0.36 ns

Figure 38 shows the timing for the bypass DCI delay mode.

DCI

DATA

tDATA

DATA VALID

WINDOW

Figure 37. Timing Diagram for Input Data Port

Table 14. Data to DCI Setup and Hold Times

DCI Delay

Bits[1:0]

Minimum Setup

Time, tS (ns)

Minimum Hold

Time, tH (ns)

Sampling

Interval (ns)

Figure 38. Timing Diagram for Input Data Port (Bypass DCI Delay Mode)

The data interface timing can be verified using the sample error

detection (SED) circuitry. See the Interface Timing Validation

section for more information.

0.12

0.45

0.57

−0.01

0.74

0.73

−0.2

1.03

0.83

−0.28

1.16

0.88

AD9146BCPZ Datasheet(PDF) 30 Page - Analog Devices

AD9146BCPZ Datasheet(HTML) 30 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL