SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(BUF)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

P

S

S

P

AMC80

SBOS559

– MAY 2011

www.ti.com

TIMING DIAGRAM

Figure 1. Serial Bus Interface Timing

TIMING CHARACTERISTICS

FAST MODE

HIGH-SPEED MODE

PARAMETER

MIN

MAX

MIN

MAX

UNITS

SCL operating frequency

10

400

10

3400

kHz

Bus free time between STOP and START conditions

600

160

ns

Hold time after repeated START condition. After this

600

160

ns

period, the first clock is generated.

Repeated START condition setup time

600

160

ns

STOP condition setup time

600

160

ns

Data hold time

ns

Data setup time

100

10

ns

Clock low period

1300

160

ns

Clock high period

600

60

ns

Clock/Data input rise time

300

160

ns

Clock/Data input fall time

300

160

ns

(1)

For cases when the fall time of SCL is less than 20 ns and/or the rise time or fall time of SDA is less than 20 ns, the hold time should be

greater than 20 ns.

(2)

For cases when the fall time of SCL is less than 10 ns and/or the rise or fall time of SDA is less than 10 ns, the hold time should be

greater than 10 ns.

6

Submit Documentation Feedback

Copyright

© 2011, Texas Instruments Incorporated

Product Folder Link(s): AMC80