OPA322SAIDBVT datasheet(4/29 Pages) TI1

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OPA322, OPA322S

OPA2322, OPA2322S

OPA4322, OPA4322S

SBOS538A

– JANUARY 2011 – REVISED MAY 2011

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ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V, or ±0.9 V to ±2.75 V (continued)

Boldface limits apply over the specified temperature range, TA = –40°C to +125°C.

At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and SHDN_x = VS+, unless otherwise noted.

OPA322, OPA322S, OPA2322,

OPA2322S, OPA4322, OPA4322S

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

Voltage output swing from

RL = 10 kΩ

both rails

Over temperature

RL = 10 kΩ

Short-circuit current

ISC

VS = 5.5 V

±65

Capacitive load drive

See Typical Characteristics

Open-loop output resistance

IO = 0 mA, f = 1 MHz

POWER SUPPLY

Specified voltage range

1.8

5.5

Quiescent current per amplifier

IO = 0 mA, VS = +5.5 V

OPA322, OPA322S

1.6

1.8

Over temperature

TBD

OPA2322, OPA2322S

1.5

1.75

Over temperature

1.85

OPA4322, OPA4322S

1.45

1.65

Over temperature

TBD

Power-on time

VS+ = 0 V to 5 V, to 90% IQ level

μs

SHUTDOWN(2)

VS = 1.8 V to 5.5 V

Quiescent current, per amplifier

IQSD

All amplifiers disabled, SHDN = VS–

0.1

µA

SHDN_A = VS–, SHDN_B = VS+

1.6

OPA2322S only

SHDN_A = VS+, SHDN_B = VS–

1.6

High voltage (enabled)

VIH

Amplifier enabled

0.7

× VS+

5.5

Low voltage (disabled)

VIL

Amplifier disabled

0.3

× VS+

Amplifier enable time(3)

tON

G = 1, VOUT = 0.9 × VS/2, full shutdown

(4)

µs

Amplifier enable time,(3)

tON

Partial shutdown(4)

µs

OPA2322S only

Amplifier disable time(3)

tOFF

G = 1, VOUT = 0.1 × VS/2

µs

VIH = 5.0 V

0.13

µA

SHDN pin input bias current (per pin)

VIL = 0 V

0.04

µA

TEMPERATURE

Specified range

–40

+125

°C

Operating range

–40

+150

°C

(2)

Ensured by design and characterization; not production tested.

(3)

Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

(4)

Full shutdown refers to the dual OPA2322S having both channels A and B disabled (SHDN_A = SHDN_B = VS–) and the quad

OPA4322S having all channels A to D disabled (SHDN_A/B = SHDN_C/D = VS–). For partial shutdown, only one SHDN pin is exercised;

in this mode, the internal biasing and oscillator remain operational and the enable time is shorter.

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