TPS62730 datasheet(21/25 Pages) TI1

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GND

OUT

Totalarea

islessthan

12mm²

TPS62730

www.ti.com

SLVSAC3

– MAY 2011

These are the basic signals that need to be measured when evaluating a switching converter. When the

switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the

regulation loop may be unstable. This is often a result of board layout and/or L-C combination.

As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between

the application of the load transient and the turn on of the High Side MOSFET, the output capacitor must supply

all of the current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR

is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge CO generating a feedback error

signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted when

the device operates in PWM mode.

During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the

converter

’s stability. Without any ringing, the loop has usually more than 45° of phase margin.

Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET

rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,

load current range, and temperature range.

LAYOUT CONSIDERATIONS

As for all switching power supplies, the layout is an important step in the design. Especially RF designs demand

careful attention to the PCB layout. Care must be taken in board layout to get the specified performance. If the

layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as

EMI problems and interference with RF circuits. It is critical to provide a low inductance, impedance ground path.

Therefore, use wide and short traces for the main current paths. The input capacitor should be placed as close

as possible to the IC pins as well as the inductor and output capacitor. Use a common Power GND node and a

different node for the Signal GND to minimize the effects of ground noise. Keep the common path to the GND

PIN, which returns the small signal components and the high current of the output capacitors as short as

possible to avoid ground noise. The VOUT line should be connected to the output capacitor and routed away

from noisy components and traces (e.g. SW line).

Figure 33. Recommended PCB Layout for TPS62730

TPS62730 Datasheet(PDF) 21 Page - Texas Instruments