MAX5965AEAX datasheet(13/54 Pages) MAXIM

13 / 54 page

High-Power, Quad, Monolithic, PSE Controllers

for Power over Ethernet

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Pin Description

NAME

FUNCTION

RESET

Hardware Reset. Pull RESET low for at least 300µs to reset the device. All internal registers reset to their

default value. The address (A0–A3), and AUTO and MIDSPAN input-logic levels latch on during low-to-

high transition of RESET. RESET is internally pulled up to VDD with a 50k

Ω resistor.

MIDSPAN

Midspan Mode Input. An internal 50k

Ω pulldown resistor to DGND sets the default mode to endpoint PSE

operation (power-over-signal pairs). Pull MIDSPAN to VDIG to set midspan operation. The MIDSPAN value

latches after the device is powered up or reset (see the PD Detection section).

INT

Open-Drain Interrupt Output. INT goes low whenever a fault condition exists. Reset the fault condition

using software or by pulling RESET low (see the Interrupt section for more information about interrupt

management).

SCL

Serial Interface Clock Line Input

SDAOUT

Serial Output Data Line. Connect the data line optocoupler input to SDAOUT (see the Typical Operating

Circuits). Connect SDAOUT to SDAIN if using a 2-wire, I

2C-compatible system.

Pin Configuration

OSC

AUTO

OUT1

GATE1

SENSE1

OUT2

GATE4

GATE2

SENSE2

VEE

OUT3

GATE3

SENSE3

OUT4

DET4

DET3

DET2

DET1

SDAIN

SDAOUT

SCL

MIDSPAN

SSOP

TOP VIEW

MAX5965A

MAX5965B

SENSE4

AGND

VDD

DGND

RESET

INT

SHD1

SHD2

SHD3

SHD4

MAX5965AEAX Datasheet(PDF) 13 Page - Maxim Integrated Products

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