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ACS8510 Datasheet(PDF) 49 Page - Semtech Corporation

Part # ACS8510
Description  Synchronous Equipment Timing Source for SONET or SDH Network Elements
PDF  69 Pages
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

ACS8510 Datasheet(HTML) 49 Page - Semtech Corporation

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Revision 2.07/Jan 2001 ã2001 Semtech Corp
www.semtech.com
49
ACS8510 SETS
ADVANCED COMMUNCIATIONS
FINAL
I6POS
I6NEG
I5NEG
I5POS
T06POS
T06NEG
T07POS
T07NEG
ZO=50
Ω
ZO=50
Ω
ZO=50
Ω
ZO=50
Ω
ZO=50
Ω
ZO=50
Ω
100R
ZO=50
Ω
ZO=50
Ω
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
51.84, 77.76 or
155.52 MHz
51.84, 77.76 or
155.52 MHz
8kHz, 1.544/2.048,
6.48, 19.44, 38.88,
19.44, 38.88, 155.52,
311.04 MHz & DIG1
19.44, 51.84, 77.76,
155.52 MHz
100R
100R
100R
Recommended line termination for LVDS Input/Output ports
The Alternate Mark Inversion (AMI) signal is DC balanced and consists of positive and negative
pulses with a peak to peak voltage of 2.0 +/- 0.2V.
The electrical specifications are taken from option a) of Table 2/G.703 - Digital 64kbit/s centralized
clock interface, from ITU G.703.
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The electrical characteristics of 64kbits/s interface are as follows;
Nominal bit rate: 64kbit/s. The tolerance is determined by the network clock stability.
There should be a symmetrical pair carrying the composite timing signal (64kHz and 8kHz). The
use of transformers is recommended.
Over-voltage protection requirement; refer to Recommendation K.41.
Code conversion rules;
The data signals are coded in AMI code with 100% duty cycle. The composite clock timing signals
convey the 64kHz bit-timing information using AMI coding with a 50% to 70% duty ratio and the
8kHz octet phase information by introducing violations in the code rule. The structure of the
signals and voltage levels are shown in Figure 9 and Figure 10.
Across operating conditions, unless otherwise stated
DC CHARACTERISTICS: AMI Input/Output pad.



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