PCA9505 datasheet(23/34 Pages) NXP

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PCA9505_9506

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Product data sheet

Rev. 4 — 3 August 2010

23 of 34

NXP Semiconductors

PCA9505/06

40-bit I2C-bus I/O port with RESET, OE and INT

[1]

Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held

LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.

[2]

tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[3]

tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

[4]

A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to

bridge the undefined region SCL’s falling edge.

[5]

The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum specified tf.

[6]

Cb = total capacitance of one bus line in pF.

[7]

Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

Reset

tw(rst)

reset pulse width

trec(rst)

reset recovery time

trst

reset time

100

Table 11.

Dynamic characteristics …continued

Symbol

Parameter

Conditions

Standard mode

I2C-bus

Fast mode I2C-bus

Unit

Min

Max

Min

Max

Fig 16. Definition of timing on the I2C-bus

tSP

tBUF

tHD;STA

tLOW

tHD;DAT

tHIGH

tSU;DAT

tSU;STA

tHD;STA

tSU;STO

SDA

SCL

002aaa986

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