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PCA9561 Datasheet(PDF) 12 Page - NXP Semiconductors |
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PCA9561 Datasheet(HTML) 12 Page - NXP Semiconductors |
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12 / 17 page  Philips Semiconductors Product data sheet PCA9561 Quad 6-bit multiplexed I2C EEPROM DIP switch 2004 May 17 12 AC CHARACTERISTICS SYMBOL PARAMETER LIMITS UNIT SYMBOL PARAMETER MIN. TYP. MAX. UNIT MUX_IN ⇒ MUX_OUT tPLH LOW-to-HIGH transition time — 28 40 ns tPHL HIGH-to-LOW transition time — 8 15 ns Select ⇒ MUX_OUT tPLH LOW-to-HIGH transition time — 30 43 ns tPHL HIGH-to-LOW transition time — 10 15 ns tR Output rise time 1.0 — 3 ns/V tF Output fall time 1.0 — 3 ns/V CL Test load capacitance on outputs — — — pF SYMBOL PARAMETER STANDARD-MODE I2C-BUS FAST-MODE I2C-BUS UNIT MIN MAX MIN MAX fSCL SCL clock frequency 0 100 0 400 kHz tBUF Bus free time between a STOP and START condition 4.7 — 1.3 — µs tHD;STA Hold time (repeated) START condition After this period, the first clock pulse is generated 4.0 — 0.6 — µs tLOW LOW period of the SCL clock 4.7 — 1.3 — µs tHIGH HIGH period of the SCL clock 4.0 — 0.6 — µs tSU;STA Set-up time for a repeated START condition 4.7 — 0.6 — µs tHD;DAT Data hold time 01 3.45 01 0.9 µs tSU;DAT Data set-up time 250 — 100 — ns tr Rise time of both SDA and SCL signals — 1000 20 + 0.1Cb2 300 ns tf Fall time of both SDA and SCL signals — 300 20 + 0.1Cb2 300 ns tSU;STO Set-up time for STOP condition 4.0 — 0.6 — µs Cb Capacitive load for each bus line — 400 — 400 pF tSP Pulse width of spikes which must be suppressed by the input filter — 50 — 50 ns NOTES: 1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 2. Cb = total capacitance of one bus line in pF. tSP tBUF tHD;STA P P S tLOW tR tHD;DAT tF tHIGH tSU;DAT tSU;STA Sr tHD;STA tSU;STO SDA SCL SU00645 Figure 10. Definition of timing |
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