Philips Semiconductors

Product data sheet

PCA9564

2006 Sep 01

25

LIMITS

SYMBOL

PARAMETER

Min

Max

UNIT

Reset Timing (See Figure 19)

Reset pulse width

10

—

ns

Time to reset

250

—

ns

Reset recovery time

0

—

ns

Bus Timing (See Figure 20, 21)

A0–A1 setup time to RD, WR LOW

0

—

ns

A0–A hold time from RD, WR LOW

9

—

ns

CE setup time to RD, WR LOW

0

—

ns

CE Hold time from RD, WR LOW

0

—

ns

WR, RD pulse width (low time)

9

—

ns

Data valid after RD and CE LOW

—

22

ns

Data bus floating after RD or CE HIGH

—

17

ns

Data bus setup time before WR or CE HIGH (write cycle)

8

—

ns

Data hold time after WR HIGH

0

—

ns

High time between read and/or write cycles

12

—

ns

NOTES:

1. Parameters are valid over specified temperature and voltage range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of 5 ns

maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figures 20–21.

4. Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.