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AS8510

Datasheet - Detailed Descr i p ti on

7.5 Reference-Voltage

Band gap-reference voltage is used for the ADC as a reference and for the generation of the current for external temperature measurement.

7.6 Oscillators

A High-speed oscillator (HS) generates the oversampling clock. For internal state machine and Interrupt generation, a low-speed Oscillator (LS)

is also available.

7.7 Power-On Reset

The AS8510 has PORs, APOR and DPOR on analog and digital power supplies respectively. On PORs of both supplies, initialization sequence

happens and the system status is shown in state diagram (see Figure 4).

As shown in the state diagram, the system is in RESET state until DPOR output goes to logic HIGH and subsequently until APOR output goes to

logic HIGH. Once analog power supply is available, the system goes into OTP_INT state and loads the default values into the control and data

registers and goes into STOP state. If analog POR, APOR goes low at any time, the system goes into RESET state. In the STOP state, the

AS8510 can be programmed and by giving start command it starts working following the state machine.

7.8 4-Wire Serial Port Interface

The SPI interface is used as interface between the AS8510 and an external micro-controller to configure the device and access the status

information. The micro-controller begins communication with the SPI which is configured as a slave. The SPI protocol is simple and the length of

each frame is an integer multiple of bytes except when a transmission is started. Each frame has 1 command bit, 7 address/configuration bits,

and one or more data bytes. The edge of CS and the level of SCLK during the start of a SPI transaction, determine the edge on which the data is

transferred from the SPI and the edge on which the data is sampled by the slave. Table 29 describes the setting of the transfer and sampling

edges of SCLK. Figure 9 shows the falling edge and rising edge for data transfer and data sampling respectively, when SCLK is HIGH on the

falling edge of CS.

Figure 9. Protocol for Serial Data Write with Length = 1

Table 29. CS and SCLK

CS

SCLK

Description

FALL

LOW

Serial data transferred on rising edge of SPI clock. Sampled at falling edge of SPI clock.

FALL

HIGH

Serial data transferred on falling edge of SPI clock. Sampled at rising edge of SPI clock.

ANY

ANY

Serial data transfer edge is unchanged.

CS

SCLK

SDI

SDO

0

A6

A5

A4

A0

A1

A2

A3

D0

D1

D2

D3

D4

D5

D7

D6

Transfer edge

Sampling edge

Data D7 – D0 is moved

to Address A4..A0 here