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LPC4350 Datasheet(PDF) 61 Page - NXP Semiconductors |
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LPC4350 Datasheet(HTML) 61 Page - NXP Semiconductors |
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61 / 145 page ![]() LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2.1 — 23 September 2011 61 of 145 NXP Semiconductors LPC4350/30/20/10 32-bit ARM Cortex-M4/M0 microcontroller TDI J4 x G3 35 26 16 [3] I; PU I Test Data In for JTAG interface. USB0 pins USB0_DP F2 x E1 26 18 9 [7] - I/O USB0 bidirectional D+ line. USB0_DM G2 x E2 28 20 11 [7] - I/O USB0 bidirectional D line. USB0_VBUS F1 x E3 29 21 12 [7] - I/O VBUS pin (power on USB cable). USB0_ID H2 x F1 30 22 13 [8] - I Indicates to the transceiver whether connected to an A-device (LOW) or a B-device (HIGH). USB0_RREF H1 x F3 32 24 15 [8] - 12.0 k (accuracy 1 %) on-board resistor to ground for current reference. USB1 pins USB1_DP F12 x E9 129 89 59 [9] - I/O USB1 bidirectional D+ line. USB1_DM G12 x E10 130 90 60 [9] - I/O USB1 bidirectional D line. I2C-bus pins I2C0_SCL L15 x D6 132 92 62 [10] I; F I/O I2C clock input/output. Open-drain output (for I2C-bus compliance). I2C0_SDA L16 x E6 133 93 63 [10] I; F I/O I2C data input/output. Open-drain output (for I2C-bus compliance). Reset and wake-up pins RESET D9 x B6 185 128 91 [11] I; IA I External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. WAKEUP0 A9 x A4 187 130 93 [11] I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. WAKEUP1 A10 x - - - - [11] I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. WAKEUP2 C9 x - - - - [11] I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. WAKEUP3 D8 x - - - - [11] I; IA I External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. ADC pins ADC0_0/ ADC1_0/DAC E3 x A2 8 6 4 [8] I; IA I ADC input channel 0. Shared between 10-bit ADC0/1 and DAC. ADC0_1/ ADC1_1 C3 x A1 4 2 1 [8] I; IA I ADC input channel 1. Shared between 10-bit ADC0/1. ADC0_2/ ADC1_2 A4 x B3 206 143 99 [8] I; IA I ADC input channel 2. Shared between 10-bit ADC0/1. ADC0_3/ ADC1_3 B5 x A3 200 139 96 [8] I; IA I ADC input channel 3. Shared between 10-bit ADC0/1. ADC0_4/ ADC1_4 C6 x - 199 138 - [8] I; IA I ADC input channel 4. Shared between 10-bit ADC0/1. Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. Symbol Description |
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